US5345566A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for controlling dual bus system
Assignee: Hitachi Ltd
•
Filing: 1992-01-24
•
Granted: 1994-09-06
•
Expires: 2012-01-24
Abstract
Abstract A method and apparatus for controlling a dual bus system, capable of realizing high speed and continuous operation even if one of the buses of the dual bus system fails. The method and apparatus has a dual bus system, a plurality of electronic circuits connected to both buses of the dual bus system, and bus controller for providing a bus use allowance signal to one of the plurality of electronic circuits, the one electronic circuit being selected in accordance with bus occupation request signals issued from the plurality of electronic circuits requesting data transfer. If the bus occupation request signals for both buses of the dual bus system originates from the one selected electronic circuit and the outputs of the arbiters coincide, the bus use allowance signal is provided to the one selected electronic circuit for the allowance of occupying both buses of the dual bus system. A completion of data transfer at the dual bus system is determined when data transfer is completed at both buses. Continuous operation can be ensured immediately upon occurrence of a failure, and high speed operation of a computer system is possible.
Inventors
- 👤 Masayuki Tanji
- 👤 Yoshihiro Miyazaki
- 👤 Hiroaki Fukumaru
- 👤 Syoji Yamaguchi
- 👤 Koji Masui
- 👤 Hisao Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:09
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4022; G06F13/14; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
211 words
The dual bus control method having a dual bus system, a plurality of electronic circuits, each having a dual bus interface, connected to both buses of said dual bus system, and bus controllers, each of said bus controllers being connected to both of said buses and being interconnected by interactive paths, each of said bus controllers providing a bus use allowance signal through an arbiter thereof to one of said plurality of electronic circuits having issued a bus use request signal through a request line thereto, said dual bus control method comprising the steps of: providing said bus use allowance signal to said one electronic circuit for allowing occupation of both buses of said dual bus system if said bus occupation request signals for both buses of said dual bus system originate from said one selected electronic circuit and said bus use allowance signals, via said arbiter, from said bus controllers coincide with one another; determined completion of data transfer by said bus controllers at said dual by system if data transfer is completed at both buses; and when an intermittent fault occurs on one of said buses of said dual bus system and a retry operation is to be executed, a retry operation executing on the other of said buses.
Claim 2
Dependent Claim
211 words
The dual bus control method having a dual bus system, a plurality of electronic circuits, each having a dual bus interface, connected to both buses of said dual bus system, and bus controllers, each of said bus controllers being connected to both of said buses and being interconnected by interactive paths, each of said bus controllers providing a bus use allowance signal through an arbiter thereof to one of said plurality of electronic circuits having issued a bus use request signal through a request line thereto, said dual bus control method comprising the steps of: providing said bus use allowance signal to said one electronic circuit for allowing occupation of both buses of said dual bus system if said bus occupation request signals for both buses of said dual bus system originate from said one selected electronic circuit and said bus use allowance signals, via said arbiter, from said bus controllers coincide with one another; determined completion of data transfer by said bus controllers at said dual by system if data transfer is completed at both buses; and when an intermittent fault occurs on one of said buses of said dual bus system and a retry operation is to be executed, a retry operation executing on the other of said buses.
Claim 3
Dependent Claim
29 words
The dual bus control method according to claim 3, wherein an interrupt is issued between said electronic circuits when a data transfer at said dual bus system is completed.
Claim 4
Dependent Claim
90 words
The dual bus control method according to claim 1, wherein, when a solid fault occurs on one of said buses of said dual bus system, said electronic circuit having detected said solid fault informs others of said plurality of electronic circuit of an occurrence of said fault, and said bus controller stops a process of checking whether or not outputs of said arbiters coincide, and said electronic circuits stop a process of determining completion of data transfer at said dual bus system if data transfer is completed at both buses.
Claim 5
Dependent Claim
286 words
The dual bus control apparatus having a dual bus system, a plurality of electronic circuits, each having a dual bus interface, connected to both buses of said dual bus system, and bus controllers, each of said bus controllers being connected to both of said buses and being interconnected by interactive paths, each of said bus controllers providing a bus use allowance signal through the buses to one of said plurality of electronic circuits having issued a bus use request signal through request line thereto, said dual bus control apparatus comprising: two bus interface units provided to each of said plurality of electronic circuits and connected to both buses of said dual bus system, said two bus interface units sending said bus occupation request signals to said buses for the data transfer to said buses, starting data transfer to said buses when both of said bus use allowance signals are received, and terminating the bus use when data transfer to both buses is completed; and two bus arbitration controllers provided to said bus controller and connected to both buses of said dual bus system, each of said two bus arbitration controllers comprising an arbiter for selecting one of said bus occupation request signals from said plurality of electronic circuits, and a comparator for providing said bus use allowance signal for the buses of said dual bus system if two of said arbiters selected the same electronic circuit; wherein said two bus interface units of said electronic circuit are provided with a means for, when an intermittent fault occurs on one of said buses of said dual bus system and a retry operation is to be executed, executing a retry operation also on the other of said buses.
Claim 6
Dependent Claim
286 words
The dual bus control apparatus having a dual bus system, a plurality of electronic circuits, each having a dual bus interface, connected to both buses of said dual bus system, and bus controllers, each of said bus controllers being connected to both of said buses and being interconnected by interactive paths, each of said bus controllers providing a bus use allowance signal through the buses to one of said plurality of electronic circuits having issued a bus use request signal through request line thereto, said dual bus control apparatus comprising: two bus interface units provided to each of said plurality of electronic circuits and connected to both buses of said dual bus system, said two bus interface units sending said bus occupation request signals to said buses for the data transfer to said buses, starting data transfer to said buses when both of said bus use allowance signals are received, and terminating the bus use when data transfer to both buses is completed; and two bus arbitration controllers provided to said bus controller and connected to both buses of said dual bus system, each of said two bus arbitration controllers comprising an arbiter for selecting one of said bus occupation request signals from said plurality of electronic circuits, and a comparator for providing said bus use allowance signal for the buses of said dual bus system if two of said arbiters selected the same electronic circuit; wherein said two bus interface units of said electronic circuit are provided with a means for, when an intermittent fault occurs on one of said buses of said dual bus system and a retry operation is to be executed, executing a retry operation also on the other of said buses.
Claim 7
Dependent Claim
41 words
A dual bus control apparatus according to claim 4, wherein each of said plurality of electronic circuits is provided with a function for issuing an interrupt to said one of electronic circuits as a data transfer at said dual bus system.
Claim 8
Dependent Claim
84 words
The dual bus control apparatus according to claim 4, wherein said two bus interface units of said electronic circuit are provided with a function of, when a solid fault occurs on one of the buses of said dual bus system, said bus interface unit having detected said solid fault informs the other said bus interface units of an occurrence of said fault, and said comparator of said bus controller has a function of stopping a process of comparing the arbitration results from said arbiters.
Claim 9
Dependent Claim
83 words
A dual bus control apparatus, comprising: two bus controllers; two bus arbiters included in each of said bus controllers and connected to both buses of said dual bus system, each of said two bus arbiters selecting one of a plurality of electronic circuits issuing bus occupation request signals; and a comparator included in each of said bus controllers for providing said bus use allowance signal for said buses of said dual bus system if two of said arbiters select a same electronic circuit.
Claim 10
Dependent Claim
83 words
A dual bus control apparatus, comprising: two bus controllers; two bus arbiters included in each of said bus controllers and connected to both buses of said dual bus system, each of said two bus arbiters selecting one of a plurality of electronic circuits issuing bus occupation request signals; and a comparator included in each of said bus controllers for providing said bus use allowance signal for said buses of said dual bus system if two of said arbiters select a same electronic circuit.
References Cited (Backward Citations)
US4245344A
Cited
US4511959A
Cited
US4473880A
Cited
US4490785A
Cited
US4495569A
Cited
US4503535A
Cited
US4503534A
Cited
US4484273A
Cited
US4535448A
Cited
US4607365A
Cited
US4766536A
Cited
US4695952A
Cited
US4982321A
Cited
US4979100A
Cited
US5202980A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-05 | 1998-03-07 | 1998-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-05 | 2002-03-07 | 2002-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-05 | 2006-03-07 | 2006-09-06 | $7700.00 | Window Closed / Lapsed |