Multi-port processor with peripheral component interconnect port and rambus port

Claim 1

A computer system, comprising: (a) a processor having first and second ports; (b) a RAMBUS channel, coupled to the first port of the processor and to a memory, for communicating electrical signals therebetween, wherein the RAMBUS channel is a high speed bus used to attach one or more memory devices to the processor as a memory subsystem; (c) a bus, coupled to the second port of the processor and to one or more electronic devices, for communicating electrical signals therebetween; and (d) a central arbiter device, coupled to the processor and the electronic devices, for selecting by arbitration a first device coupled to the bus for actively and exclusively driving a specific electrically conductive signal connection of the bus to a logic 1 or 0 value during a first time period, and for selecting by arbitration a second device coupled to the bus for actively and exclusively driving the specific electrically conductive signal connection of the bus to a logic 1 or 0 value during a second time period following the first time period, so that the specific electrical conductive signal connection of the bus is never let floating for an extended period of time, each device that requests exclusive control of the bus having a request signal line and grant signal line connected to the central arbiter device, the request signal line indicating to the central arbiter device that the device desires use of the bus, and the grant signal line indicating to the device that access to the bus has been granted by the central arbiter device, wherein the central arbiter device further comprises arbiter parking means for asserting the grant signal line to a selected device not requesting access to the bus when no other device is requesting access to the bus, thereby effectively designating the selected device as a default owner of the bus, so that the bus will not float.

Claim 11

A method of communicating between a processor, a memory, and peripheral devices in a computer system, comprising the steps of: (a) communicating electrical signals between a processor and a memory on a RAMBUS channel coupled to a first port of the processor and to the memory, wherein the RAMBUS channel is a high speed bus used to attach one or more memory devices to the processor as a memory subsystem; (b) communicating electrical signals between the processor and one or more peripheral devices on a bus coupled to a second port of the processor and to the peripheral devices, wherein each device that requests exclusive control of the bus has a request signal line and grant signal line connected to a central arbiter device, the request signal line indicating to the central arbiter device that the device desires use of the bus, and the grant signal line indicating to the device that access to the bus has been granted by the central arbiter device; (c) selecting by arbitration a first device coupled to the bus for actively and exclusively driving a specific electrically conductive signal connection of the bus to a logic 1 or 0 value during a first time period, and selecting by arbitration a second device coupled to the bus for actively and exclusively driving the specific electrically conductive signal connection of the bus to a logic 1 or 0 value during a second time period following the first time period, so that the specific electrical conductive signal connection of the bus is never left floating for an extended period of time; and (d) arbitration parking the bus, comprising the step of asserting the grant signal line to a selected device not requesting access to the bus when no other device is requesting access to the bus, thereby effectively designating the selected device as a default owner of the bus, so that the bus will not float.

Claim 12

A method of communicating between a processor, a memory, and peripheral devices in a computer system, comprising the steps of: (a) communicating electrical signals between a processor and a memory on a RAMBUS channel coupled to a first port of the processor and to the memory, wherein the RAMBUS channel is a high speed bus used to attach one or more memory devices to the processor as a memory subsystem; (b) communicating electrical signals between the processor and one or more peripheral devices on a bus coupled to a second port of the processor and to the peripheral devices, wherein each device that requests exclusive control of the bus has a request signal line and grant signal line connected to a central arbiter device, the request signal line indicating to the central arbiter device that the device desires use of the bus, and the grant signal line indicating to the device that access to the bus has been granted by the central arbiter device; (c) selecting by arbitration a first device coupled to the bus for actively and exclusively driving a specific electrically conductive signal connection of the bus to a logic 1 or 0 value during a first time period, and selecting by arbitration a second device coupled to the bus for actively and exclusively driving the specific electrically conductive signal connection of the bus to a logic 1 or 0 value during a second time period following the first time period, so that the specific electrical conductive signal connection of the bus is never left floating for an extended period of time; and (d) arbitration parking the bus, comprising the step of asserting the grant signal line to a selected device not requesting access to the bus when no other device is requesting access to the bus, thereby effectively designating the selected device as a default owner of the bus, so that the bus will not float.