EP0503850A1
Expired / Lapsed
EP
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Microprocessor with low power bus
Assignee: AT&T Inc
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Filing: 1992-03-06
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Granted: —
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Expires: 2012-03-06
Abstract
Abstract A microprocessor provides a bus state referred to as "loop-back". This state holds the data bus at valid logic levels, without use of resistors, after a read transaction has been completed and there are no pending bus transactions. When this state is entered, the data just read from the data bus (220) is driven back onto the data bus, and the device (210, 21N) which had provided the data is placed in the tri-state (high-impedance) condition. This loop-back feature, combined with the fact that all other outputs are held at their previous values, provides for near-zero power dissipation on the bus. The inventive technique avoids the use of pull-up resistors (R₁... R n ), which are provided on prior art tri-state busses (C₁ ... C n ) to ensure that the busses do not float and enter the threshold region where high power dissipation occurs.
Inventors
- 👤 Robert Thomas Franzo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 21:16
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
88 words
An integrated circuit comprising: means (63) for sending data signals, and means (60) for receiving data signals, over a bus (220), and means (200) for requesting data to be sent over the bus, and means (221) for receiving acknowledgement of the receipt of data sent over the bus: characterized in that said integrated circuit further comprises means (62) for maintaining valid on said bus the last-received data, when said integrated circuit receives the acknowledgement of the receipt of said last-received data and no further bus transactions are pending.
Claim 2
Dependent Claim
66 words
The integrated circuit of claim 1 wherein said means for sending data signals comprises a tri-state output buffer (63) and said means for receiving data signals comprises an input buffer (60), and further characterized in that said means for maintaining valid on said bus the last-received data comprises multiplexer means (62) for coupling the output of said input buffer to be input of said output buffer.
Claim 3
Dependent Claim
34 words
The integrated circuit of claim 2 wherein said means for receiving data signals further comprises an input latch (61), wherein the output of said input buffer is coupled to said multiplexer through said latch.
Claim 4
Dependent Claim
23 words
The integrated circuit of any of the preceding claims wherein said means for receiving data signals comprises a field effect transistor input stage.
Claim 5
Dependent Claim
18 words
The integrated circuit of claim 4 wherein said field effect transistor input stage includes a CMOS input buffer.
Claim 6
Dependent Claim
18 words
The integrated circuit of any of the preceding claims wherein said bus is external to said integrated circuit.
Claim 7
Dependent Claim
13 words
The integrated circuit of claim 6 wherein said bus is a multi-conductor bus.
Claim 8
Dependent Claim
13 words
The integrated circuit of claim 6 wherein said bus is a single-conductor bus.
Claim 9
Dependent Claim
110 words
A data system comprising a first master device (300) and a multiplicity of slave devices (330,33M) that communicate over a bus (341), wherein said master device comprises: means (63) for sending data signals, and means (60) for receiving data signals, over said bus, and means for requesting data to be sent over the bus, and means (342) for receiving acknowledgement of the transfer of data sent over the bus; characterized in that said first master device further comprises means (62) for maintaining valid on said bus the last-received data, when said first master device receives acknowledgement of the transfer of said last-received data and no further bus transactions are pending.
Claim 10
Dependent Claim
141 words
The data system of claim 9 further comprising a second master device (30N) that communicates over said bus, wherein said second master device comprises: means (63) for sending data signals, and means (60) for receiving data signals, over a bus, and means for requesting data to be sent over the bus, and means (342) for receiving acknowledgement of the transfer of data sent over the bus; and further characterized in that said second master device further comprises means (62) for maintaining valid on said bus the last-received data, when said second master device receives acknowledgement of the transfer of said last-received data and no further bus transations are pending; and wherein said data system further comprises arbitration means (320) for choosing which of said first (300) and second (30N) master devices has access to said bus (341) at a given time.
Claim 11
Dependent Claim
78 words
The data system of claim 9 or claim 10 wherein the or each said means for sending data signals comprises a tri-state output buffer (63) and the or each said means for receiving data signals comprises an input buffer (60), and further characterized in that the or each said means for maintaining valid on said bus the last-received data comprises multiplexer means (62) for coupling the output of said input buffer to the input of said output buffer.
Claim 12
Dependent Claim
39 words
The data system of claim 11 wherein the or each said means for receiving data signals further comprises an input latch (61), wherein the output of said input buffer (60) is coupled to said multiplexer (62) through said latch.
Claim 13
Dependent Claim
27 words
The data system of any of claims 9 to 12 wherein the or each said means for receiving data signals comprises a field effect transistor input stage.
Claim 14
Dependent Claim
18 words
The data system of claim 13 wherein said field effect transistor input stage includes a CMOS input buffer.
Claim 15
Dependent Claim
41 words
The data system of claim 10 wherein said first master device is formed in a first integrated circuit, said second master device is formed in a second integrated circuit, and said bus is external to said first and second integrated circuits.
Claim 16
Dependent Claim
14 words
The data system of claim 15 wherein said bus (341) is a multi-conductor bus.
Claim 17
Dependent Claim
14 words
The data system of claim 15 wherein said bus (341) is a single-conductor bus.
References Cited (Backward Citations)
US4551821A
Cited
EP0341841A2
Cited
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