Internal ESD protection circuit for semiconductor devices

Abstract

Abstract An internal electrostatic discharge (ESD) protection circuit for semiconductor devices defines a structure for protecting adjacent n-channel devices. The first n-channel device includes a pair of n+ regions defining source and drain regions wherein the drain region is connected to a positive power supply terminal (V DD ). The second, adjacent, n-channel device also includes a pair of n+ regions forming source and drain regions, respectively, wherein the source region of the second n-channel device is connected to a negative power supply terminal (V SS ). The drain of the first n-channel device is laterally spaced, and isolated from the source of the second n-channel device by a thick field oxide region. The novel structure includes forming an N-conductivity type well that substantially overlaps the drain n+ region of the first n-channel device and extends toward the n+ region that forms the source of the second n-channel device. The N-well is doped to a lower density than the n+ regions, and further, is formed into the substrate to a depth that is substantially larger than the depth of the n+ regions. The N-well substantially increases the junction breakdown voltage of the device. Alternately, a p+ conductivity guard ring is disposed intermediate the n+ region forming the drain of the first n-channel device, and the n+ region forming the source of the second n-channel device to thereby reduce the current gain of a parasitic NPN bipolar transistor formed between the two n-channel devices. The decreased current gain prevents snapback triggered by an ESD event.

Inventors

• 👤 Ta-Lee Yu

Bibliographic Details