Semiconductor CMOS memory device with separately biased wells

Abstract

Abstract Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

Inventors

• 👤 Shinji Nakazato
• 👤 Hideaki Uchida
• 👤 Yoshikazu Saito
• 👤 Masahiro Yamamura
• 👤 Yutaka Kobayashi
• 👤 Takahide Ikeda
• 👤 Ryoichi Hori
• 👤 Goro Kitsukawa
• 👤 Kiyoo Itoh
• 👤 Nobuo Tanba
• 👤 Takao Watanabe
• 👤 Katsuhiro Shimohigashi
• 👤 Noriyuki Homma

Bibliographic Details