US4497043A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1982-04-26
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Granted: 1985-01-29
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Expires: 2002-04-26
Abstract
Abstract A semiconductor memory device which comprises a memory section formed of a first substrate region of a first conductivity type and a first MOS transistor of a second conductivity type which is formed in the first substrate region to act as a transfer gate; and a peripheral circuit constituted by a second MOS transistor of a first conductivity type and a third MOS transistor of a second conductivity type. A second substrate region of a second conductivity type in which the second MOS transistor is formed substantially surrounds the memory section.
Inventors
- 👤 Tetsuya Iizuka
- 👤 Hisashi Hara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:30
CPC Classifications
H; H10; H10B; H10B12/00; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
103 words
A semiconductor memory device comprising: a semiconductor body of a first conductivity type; first and second semiconductor regions of a second conductivity type formed in the surface of said semiconductor body; a memory section having at least one MOS transistor of a first channel type formed in the surface of said first semiconductor region and acting as a transfer gate; and a peripheral circuit including at least a second MOS transistor of a second channel type formed in the surface of said semiconductor body and a third MOS transistor of said first channel type formed in the surface of said second semiconductor region.
Claim 2
Dependent Claim
103 words
A semiconductor memory device comprising: a semiconductor body of a first conductivity type; first and second semiconductor regions of a second conductivity type formed in the surface of said semiconductor body; a memory section having at least one MOS transistor of a first channel type formed in the surface of said first semiconductor region and acting as a transfer gate; and a peripheral circuit including at least a second MOS transistor of a second channel type formed in the surface of said semiconductor body and a third MOS transistor of said first channel type formed in the surface of said second semiconductor region.
Claim 3
Dependent Claim
41 words
The semiconductor memory device according to claim 1, further including means for applying a voltage to said semiconductor body and said first semiconductor region wherein a PN junction defined by said semiconductor body and said first semiconductor region are reversed biased.
Claim 4
Dependent Claim
58 words
The semiconductor memory device according to claim 1, wherein said semiconductor body is formed of a semiconductor substrate and an epitaxially grown layer of said first conductivity type formed on the semiconductor substrate of said first conductivity type, and said first semiconductor region is a well region of said second conductivity type formed in said epitaxially grown layer.
Claim 5
Dependent Claim
27 words
The semiconductor memory device according to claim 3, wherein an impurity concentration in the semiconductor substrate is higher than an impurity concentration in said epitaxially grown layer.
Claim 6
Dependent Claim
45 words
The semiconductor memory device according to claim 3, wherein the well region of the second conductivity type contacts the semiconductor substrate, and the third MOS transistor is formed in an epitaxially grown layer of the first conductivity type substantially isolated from said second semiconductor region.
Claim 7
Dependent Claim
109 words
A semiconductor memory device comprising: a semiconductor body of a first conductivity type; a memory section having at least one MOS transistor of a first channel type formed in the surface of said semiconductor body and acting as a transfer gate; a semiconductor region of a second conductivity type formed in the surface of said semiconductor body substantially surrounding said memory section; and a peripheral circuit including at least one MOS transistor of a second channel type formed in the surface of said semiconductor region and at least one MOS transistor of said first channel type formed in the surface of said semiconductor body and outside said semiconductor region.
Claim 8
Dependent Claim
109 words
A semiconductor memory device comprising: a semiconductor body of a first conductivity type; a memory section having at least one MOS transistor of a first channel type formed in the surface of said semiconductor body and acting as a transfer gate; a semiconductor region of a second conductivity type formed in the surface of said semiconductor body substantially surrounding said memory section; and a peripheral circuit including at least one MOS transistor of a second channel type formed in the surface of said semiconductor region and at least one MOS transistor of said first channel type formed in the surface of said semiconductor body and outside said semiconductor region.
Claim 9
Dependent Claim
130 words
A semiconductor memory device comprising: a semiconductor body of a first conductivity type; first and second semiconductor regions of a second conductivity type separately formed in the surface of said semiconductor body; a memory section having at least one MOS transistor of a first channel type formed in the surface of said first semiconductor region and acting as a transfer gate; a peripheral circuit including at least one MOS transistor of said first channel type formed in the surface of said second semiconductor region; and a third semiconductor region of said first conductivity type formed in the surface of said semiconductor body surrounding said first semiconductor region and having a higher impurity concentration than said semiconductor body and a predetermined potential for absorbing minority carriers generated in said semiconductor body.
Claim 10
Dependent Claim
130 words
A semiconductor memory device comprising: a semiconductor body of a first conductivity type; first and second semiconductor regions of a second conductivity type separately formed in the surface of said semiconductor body; a memory section having at least one MOS transistor of a first channel type formed in the surface of said first semiconductor region and acting as a transfer gate; a peripheral circuit including at least one MOS transistor of said first channel type formed in the surface of said second semiconductor region; and a third semiconductor region of said first conductivity type formed in the surface of said semiconductor body surrounding said first semiconductor region and having a higher impurity concentration than said semiconductor body and a predetermined potential for absorbing minority carriers generated in said semiconductor body.
Claim 11
Dependent Claim
102 words
A semiconductor memory device comprising: a semiconductor body of a first conductivity type; a memory section having at least one MOS transistor of a first channel type formed in the surface of said semiconductor body and acting as a transfer gate; a semiconductor region of a second conductivity type formed in the surface of said semiconductor body substantially surrounding said memory section and a potential for absorbing minority carriers generated in said semiconductor body; and a peripheral circuit including at least one MOS transistor of said first channel type formed in the surface of said semiconductor body and outside said semiconductor region.
Claim 12
Dependent Claim
102 words
A semiconductor memory device comprising: a semiconductor body of a first conductivity type; a memory section having at least one MOS transistor of a first channel type formed in the surface of said semiconductor body and acting as a transfer gate; a semiconductor region of a second conductivity type formed in the surface of said semiconductor body substantially surrounding said memory section and a potential for absorbing minority carriers generated in said semiconductor body; and a peripheral circuit including at least one MOS transistor of said first channel type formed in the surface of said semiconductor body and outside said semiconductor region.
References Cited (Backward Citations)
US4228527A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-29 | 1988-07-30 | 1989-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-29 | 1992-07-30 | 1993-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-29 | 1996-07-30 | 1997-01-29 | $7700.00 | Window Closed / Lapsed |