Dynamic semiconductor memory device with higher density bit line/word line layout

Claim 2

A semiconductor device, comprising: a semiconductor substrate; a plurality of word lines arranged to extend in a first direction along the semiconductor substrate; a plurality of bit lines arranged to extend in a second direction, perpendicular to the first direction, along the semiconductor substrate; a bit line contact formed between first and second adjacent word lines; a first storage node contact formed adjacent the first word line, and a second storage node contact formed adjacent the second word line, the first and second storage node contacts forming storage capacitors.

Claim 3

The semiconductor device according to claim 1, wherein the bit line contact includes a polysilicon layer.

Claim 4

The semiconductor device according to claim 1, further comprising a BPSG film laminated on the bit line.

Claim 5

The semiconductor device according to claim 2, further comprising a BPSG film laminated on the bit line.

Claim 6

The semiconductor device according to claim 1, further comprising a capacitor storage film formed on the first and second storage node contacts.

Claim 7

The semiconductor device according to claim 5, further comprising a plate polysilicon layer covering the capacitor storage film.

Claim 8

The semiconductor device according to claim 2, further comprising a capacitor storage film formed on the first and second storage node contacts.

Claim 9

The semiconductor device according to claim 7, further comprising a plate polysilicon layer covering the capacitor storage film.

Claim 10

The semiconductor device according to claim 1, further comprising an isolation trench formed in the semiconductor substrate.

Claim 11

The semiconductor device according to claim 1, further comprising a storage charge contact plug filled with polysilicon formed adjacent the first word line, the polysilicon extending to the first storage node contact.

Claim 12

A dynamic semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells each formed of a MOS transistor and a capacitor which is formed on said semiconductor substrate and has a storage node contact; a plurality of word lines formed on said semiconductor substrate, spaces being provided between adjacent word lines and including odd-numbered and even-numbered spaces; a plurality of bit lines formed on said semiconductor substrate to intersect said word lines, said bit lines including odd-numbered and even-numbered bit lines; and a plurality of bit line contacts formed under said bit lines with each respective bit line contact being commonly used by two respective memory cells of said plurality of memory cells, two respective storage node contacts of said two respective memory cells connected to each respective bit line contact being arranged across each bit line connected to said respective bit line contact, a combination of each respective bit line contact and said two memory cells forming an element region, those of said bit line contacts which electrically connect to said even-numbered bit lines to said memory cells being arranged in said even-numbered spaces and those of said bit line contacts which electrically connect to said odd-numbered bit lines to said memory cells being arranged in said odd-numbered spaces, wherein respective element regions are arranged in parallel, said storage node contact of one of said two memory cells connected to a first bit line contact and said storage node contact of one of said two memory cells connected to a second bit line contact, which is formed under the same bit line as said first bit line contact and is adjacent thereto, are arranged across the bit line, and said storage node contacts of said memory cells, which are respectively connected to an adjacent two of said bit line contacts connected to the same bit line and which are respectively connected to an adjacent two of said word lines, are arranged to sandwich the same bit line, and are arranged at the same space between said adjacent two of said word lines.

Claim 13

A dynamic semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells each formed of a MOS transistor and a capacitor which is formed on said semiconductor substrate and has a storage node contact; a plurality of word lines formed on said semiconductor substrate, spaces being provided between adjacent word lines and including odd-numbered and even-numbered spaces; a plurality of bit lines formed on said semiconductor substrate to intersect said word lines, said bit lines including odd-numbered and even-numbered bit lines; and a plurality of bit line contacts formed under said bit lines with each respective bit line contact being commonly used by two respective memory cells of said plurality of memory cells, two respective storage node contacts of said two respective memory cells connected to each respective bit line contact being arranged across each bit line connected to said respective bit line contact, a combination of each respective bit line contact and said two memory cells forming an element region, those of said bit line contacts which electrically connect to said even-numbered bit lines to said memory cells being arranged in said even-numbered spaces and those of said bit line contacts which electrically connect to said odd-numbered bit lines to said memory cells being arranged in said odd-numbered spaces, wherein respective element regions are arranged in parallel, said storage node contact of one of said two memory cells connected to a first bit line contact and said storage node contact of one of said two memory cells connected to a second bit line contact, which is formed under the same bit line as said first bit line contact and is adjacent thereto, are arranged across the bit line, and said storage node contacts of said memory cells, which are respectively connected to an adjacent two of said bit line contacts connected to the same bit line and which are respectively connected to an adjacent two of said word lines, are arranged to sandwich the same bit line, and are arranged at the same space between said adjacent two of said word lines.

Claim 14

The dynamic semiconductor memory device according to claim 11, wherein said bit lines and word lines are respectively arranged at predetermined spaces.

Claim 15

The dynamic semiconductor memory device according to claim 11, wherein said bit lines and said word lines perpendicularly intersect each other.

Claim 16

The dynamic semiconductor memory device according to claim 11, wherein a pitch of adjacent bit lines is larger than a pitch of adjacent word lines.

Claim 17

The dynamic semiconductor memory device according to claim 14, wherein the pitch of adjacent bit lines is 1.5 times the pitch of adjacent word lines.

Claim 18

A dynamic semiconductor memory device according to claim 11, wherein said memory cells are formed in an active region which is electrically separated by an element isolation layer, a pair of said word lines which are electrically independent passing through said active region, and a transfer region is formed at a cross point of said active region and one of said word lines.

Claim 19

A dynamic semiconductor memory device according to claim 16, wherein one of said bit line contacts and two storage node contacts are formed in said active region, and one of said bit line contacts is arranged by crossing said word lines.

Claim 20

A dynamic semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells each formed of a MOS transistor and a capacitor which is formed on said semiconductor substrate and has a storage node contact; a plurality of word lines formed on said semiconductor substrate, spaces being provided between adjacent word lines and including odd-numbered and even-numbered spaces; a plurality of bit lines formed on said semiconductor substrate to intersect said word lines, said bit lines including odd-numbered and even-numbered bit lines; and a plurality of bit line contacts formed under said bit lines with each respective bit line contact being commonly used by two respective memory cells of said plurality of memory cells, two respective storage node contacts of said two respective memory cells connected to each respective bit line contact being arranged across each bit line connected to said respective bit line contact, a combination of each respective bit line contact and said two memory cells forming an element region, those of said bit line contacts which electrically connect to said even-numbered bit lines to said memory cells being arranged in said even-numbered spaces and those of said bit line contacts which electrically connect to said odd-numbered bit lines to said memory cells being arranged in said odd-numbered spaces, wherein element regions of alternate bit lines are arranged in parallel and element regions of adjacent bit lines are alternately arranged, said storage node contact of one of said two memory cells connected to a first bit line contact and said storage node contact of one of said two memory cells connected to a second bit line contact, which is formed under the same bit line as said first bit line contact and is adjacent thereto, are arranged across the bit line, and said storage node contacts of said memory cells, which are respectively connected to an adjacent two of said bit line contacts connected to the same bit line and which are respectively connected to an adjacent two of said word lines, are arranged to sandwich the same bit line, and are arranged at the same space between said adjacent two of said word lines.

Claim 21

A dynamic semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells each formed of a MOS transistor and a capacitor which is formed on said semiconductor substrate and has a storage node contact; a plurality of word lines formed on said semiconductor substrate, spaces being provided between adjacent word lines and including odd-numbered and even-numbered spaces; a plurality of bit lines formed on said semiconductor substrate to intersect said word lines, said bit lines including odd-numbered and even-numbered bit lines; and a plurality of bit line contacts formed under said bit lines with each respective bit line contact being commonly used by two respective memory cells of said plurality of memory cells, two respective storage node contacts of said two respective memory cells connected to each respective bit line contact being arranged across each bit line connected to said respective bit line contact, a combination of each respective bit line contact and said two memory cells forming an element region, those of said bit line contacts which electrically connect to said even-numbered bit lines to said memory cells being arranged in said even-numbered spaces and those of said bit line contacts which electrically connect to said odd-numbered bit lines to said memory cells being arranged in said odd-numbered spaces, wherein element regions of alternate bit lines are arranged in parallel and element regions of adjacent bit lines are alternately arranged, said storage node contact of one of said two memory cells connected to a first bit line contact and said storage node contact of one of said two memory cells connected to a second bit line contact, which is formed under the same bit line as said first bit line contact and is adjacent thereto, are arranged across the bit line, and said storage node contacts of said memory cells, which are respectively connected to an adjacent two of said bit line contacts connected to the same bit line and which are respectively connected to an adjacent two of said word lines, are arranged to sandwich the same bit line, and are arranged at the same space between said adjacent two of said word lines.

Claim 22

The dynamic semiconductor memory device according to claim 18, wherein said bit lines and word lines are respectively arranged at predetermined spaces.

Claim 23

The dynamic semiconductor memory device according to claim 18, wherein said bit lines and said word lines perpendicularly intersect each other.

Claim 24

The dynamic semiconductor memory device according to claim 18, wherein a pitch of adjacent bit lines is larger than a pitch of adjacent word lines.

Claim 25

The dynamic semiconductor memory device according to claim 21, wherein the pitch of adjacent bit lines is 1.5 times the pitch of adjacent word lines.

Claim 26

A dynamic semiconductor memory device according to claim 18, wherein said memory cells are formed in an active region which is electrically separated by an element isolation layer, a pair of said word lines which are electrically independent passing through said active region, and a transfer region is formed at a cross point of said active region and one of said word lines.

Claim 27

A dynamic semiconductor memory device according to claim 23, wherein one of said bit line contacts and two storage node contacts are formed in said active region, and one of said bit line contacts is arranged by crossing said word lines.

Claim 28

A dynamic semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells each formed of a MOS transistor and a capacitor which is formed on said semiconductor substrate and has a storage node contact; a plurality of word lines formed on said semiconductor substrate, spaces being provided between adjacent word lines and including odd-numbered and even-numbered spaces; a plurality of bit lines formed on said semiconductor substrate to intersect said word lines, said bit lines including odd-numbered and even-numbered bit lines; and a plurality of bit line contacts formed under said bit lines with each respective bit line contact being commonly used by two respective memory cells of said plurality of memory cells, two respective storage node contacts of said two respective memory cells connected to each respective bit line contact being arranged at a same space between each bit line connected to said each respective bit line contact and a bit line adjacent thereto, those of said bit line contacts which electrically connect to said even-numbered bit lines to said memory cells being arranged in said even-numbered spaces and those of said bit line contacts which electrically connect to said odd-numbered bit lines to said memory cells being arranged in said odd-numbered spaces, wherein said storage node contact of one of said two memory cells connected to a first bit line contact and said storage node contact of one of said two memory cells connected to a second bit line contact, which is formed under the same bit line as said first bit line contact and is adjacent thereto, are arranged across the bit line, and said storage node contacts of said memory cells, which are respectively connected to an adjacent two of said bit line contacts connected to the same bit line and which are respectively connected to an adjacent of said word lines, are arranged to sandwich the same bit line, and are arranged at the same space between the adjacent two of said word lines.

Claim 29

A dynamic semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells each formed of a MOS transistor and a capacitor which is formed on said semiconductor substrate and has a storage node contact; a plurality of word lines formed on said semiconductor substrate, spaces being provided between adjacent word lines and including odd-numbered and even-numbered spaces; a plurality of bit lines formed on said semiconductor substrate to intersect said word lines, said bit lines including odd-numbered and even-numbered bit lines; and a plurality of bit line contacts formed under said bit lines with each respective bit line contact being commonly used by two respective memory cells of said plurality of memory cells, two respective storage node contacts of said two respective memory cells connected to each respective bit line contact being arranged at a same space between each bit line connected to said each respective bit line contact and a bit line adjacent thereto, those of said bit line contacts which electrically connect to said even-numbered bit lines to said memory cells being arranged in said even-numbered spaces and those of said bit line contacts which electrically connect to said odd-numbered bit lines to said memory cells being arranged in said odd-numbered spaces, wherein said storage node contact of one of said two memory cells connected to a first bit line contact and said storage node contact of one of said two memory cells connected to a second bit line contact, which is formed under the same bit line as said first bit line contact and is adjacent thereto, are arranged across the bit line, and said storage node contacts of said memory cells, which are respectively connected to an adjacent two of said bit line contacts connected to the same bit line and which are respectively connected to an adjacent of said word lines, are arranged to sandwich the same bit line, and are arranged at the same space between the adjacent two of said word lines.

Claim 30

The dynamic semiconductor memory device according to claim 25, wherein said bit lines and word lines are respectively arranged at predetermined spaces.

Claim 31

The dynamic semiconductor memory device according to claim 25, wherein said bit lines and said word lines perpendicularly intersect each other.

Claim 32

The dynamic semiconductor memory device according to claim 25, wherein a pitch of adjacent bit lines is larger than a pitch of adjacent word lines.

Claim 33

The dynamic semiconductor memory device according to claim 28, wherein the pitch of adjacent bit lines is 1.5 times the pitch of adjacent word lines.

Claim 34

A dynamic semiconductor memory device according to claim 35, wherein said memory cells are formed in an active region which is electrically separated by an element isolation layer, a pair of said word lines which are electrically independently passing through said active region, and a transfer region is formed at a cross point of said active region and one of said word lines.

Claim 35

A dynamic semiconductor memory device according to claim 30, wherein one of said bit line contacts and two storage node contacts are formed in said active region, and one of said bit line contacts is arranged by crossing said word lines.