US5383151A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory
Assignee: Sharp Corp
•
Filing: 1993-08-02
•
Granted: 1995-01-17
•
Expires: 2013-08-02
Abstract
Abstract A dynamic random access memory includes a plurality of DRAM cell units having a bit contact region and DRAM cells formed on an active region, wherein the DRAM cells each comprised of a transistor and a capacitor connected to the transistor are arranged symmetrically to the right and left sides in a bit contact connected with the active region to form the DRAM cell unit; and the DRAM cell units are arranged with a prescribed pitch in the direction of X and arranged in the direction of Y shifted with one third of the pitch toward the direction of X.
Inventors
- 👤 Shigeo Onishi
- 👤 Kenichi Tanaka
- 👤 Keizo Sakiyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:36
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; Y; Y10; Y10S; Y10S257/00; Y10S257/905; Y10S257/907
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
140 words
A dynamic random access memory which includes a plurality of rows of DRAM cell units each having a bit contact region and DRAM cells each formed in an active region, wherein the DRAM cells, each comprised of a transistor and a capacitor connected to the transistor, are arranged symmetrically to the right and left sides of a bit contact connected with the active region to form the DRAM cell unit; and wherein each row of DRAM cell units is arranged with a prescribed uniform pitch in an X direction and further arranged in an orthogonal direction of Y shifted by about one third of the pitch in the X direction with respect to adjacent rows, whereby the prescribed uniform pitch produces uniformity in device density and is sufficiently small as to allow high integration density of said DRAM cell units.
Claim 2
Dependent Claim
140 words
A dynamic random access memory which includes a plurality of rows of DRAM cell units each having a bit contact region and DRAM cells each formed in an active region, wherein the DRAM cells, each comprised of a transistor and a capacitor connected to the transistor, are arranged symmetrically to the right and left sides of a bit contact connected with the active region to form the DRAM cell unit; and wherein each row of DRAM cell units is arranged with a prescribed uniform pitch in an X direction and further arranged in an orthogonal direction of Y shifted by about one third of the pitch in the X direction with respect to adjacent rows, whereby the prescribed uniform pitch produces uniformity in device density and is sufficiently small as to allow high integration density of said DRAM cell units.
Claim 3
Dependent Claim
38 words
The dynamic random access memory according to claim 1, wherein one capacitor disposed in a DRAM cell unit is placed between two capacitors disposed in other DRAM cell units adjacent to each other in the direction of Y.
Claim 4
Dependent Claim
20 words
The dynamic random access memory according to claim 1, wherein the capacitor includes a ferroelectric film as an insulating film.
Claim 5
Dependent Claim
38 words
The dynamic random access memory according to claim 1 wherein the DRAM cell units of each row are separated by a distance of about 1 micron and the size of each DRAM cell is about 0.25 square micron.
References Cited (Backward Citations)
US4962476A
Cited
US5033022A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-16 | 1998-07-18 | 1999-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-16 | 2002-07-18 | 2003-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-16 | 2006-07-18 | 2007-01-17 | $7700.00 | Window Closed / Lapsed |