US5033022A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device having low noise bit line structure
Assignee: NEC Corp
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Filing: 1990-04-30
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Granted: 1991-07-16
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Expires: 2010-04-30
Abstract
Abstract A semiconductor memory device having an improved digit line structure which is capable of carrying out a low-noise operation is disclosed. The semiconductor memory device has in each column a digit line pair and a sense amplifier connected to the digit line pair. Each pair of digit lines are composed of a plurality of first wirings formed of a first conductor layer and a plurality of second wirings formed of a second conductor layer isolated from the first conductor layer through an insulating layer. One of the digit lines of each digit line pair is formed by electrically connecting part of the first wiring and part of the second wiring, and the other digit line of the digit line pair is formed by electrically connecting the other part of the first wiring and the other part of the second wiring.
Inventors
- 👤 Machio Segawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:17
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; H; H10; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
199 words
A semiconductor memory device having memory cells arranged in a matrix form of rows and columns, word lines provided for the respective rows of the memory cells, digit line pairs provided for the respective column of the memory cells, and sense amplifiers connected to the respective digit line pairs, said digit line pairs being divided alternately into a first and a second groups, the digit line pairs of said first group having a first and a second wirings that sequentially extend in a first longitudinal lane in along a direction of the columns and a third and a fourth wirings that sequentially extend in a second longitudinal lane parallel to said first longitudinal lane, said first and second wirings being formed as a first conductor layer and said third and fourth wirings being formed as a second conductor layer via an insulator layer which is isolated from said first conductor layer through an insulating layer, said first and fourth wirings being electrically connected to constitute one digit line of said first group of digit line pair and said third and second wirings being electrically connected to constitute the other digit line of said first group of digit lines pair.
Claim 2
Dependent Claim
199 words
A semiconductor memory device having memory cells arranged in a matrix form of rows and columns, word lines provided for the respective rows of the memory cells, digit line pairs provided for the respective column of the memory cells, and sense amplifiers connected to the respective digit line pairs, said digit line pairs being divided alternately into a first and a second groups, the digit line pairs of said first group having a first and a second wirings that sequentially extend in a first longitudinal lane in along a direction of the columns and a third and a fourth wirings that sequentially extend in a second longitudinal lane parallel to said first longitudinal lane, said first and second wirings being formed as a first conductor layer and said third and fourth wirings being formed as a second conductor layer via an insulator layer which is isolated from said first conductor layer through an insulating layer, said first and fourth wirings being electrically connected to constitute one digit line of said first group of digit line pair and said third and second wirings being electrically connected to constitute the other digit line of said first group of digit lines pair.
Claim 3
Dependent Claim
111 words
A semiconductor memory device as claimed in claim 1, wherein each of said second group of digit line pairs having a fifth to a seventh wirings sequentially formed as said first conductor layers in a third longitudinal lane in a direction of the and an eighth to a tenth wirings sequentially formed as said second conductor layers in a longitudinal zone parallel to said third longitudinal lane, said fifth, ninth and seventh wirings being electrically connected to constitute one digit line of said second group of digit line pair, said eighth, sixth and tenth wirings being electrically connected constituting the other digit line of said second group of digit line pair.
Claim 4
Dependent Claim
32 words
A semiconductor memory device as claimed in claim 1, wherein said first to fourth wirings have lengths substantially equal to x12 where x is the length of each of said digit lines.
Claim 5
Dependent Claim
47 words
A semiconductor memory device as claimed in claim 1, wherein said fifth, seventh, eighth and tenth wirings have respective lengths substantially equal to x14, and said sixth and ninth wirings have lengths substantially equal to x12 where x is the length of each of said digit lines.
Claim 6
Dependent Claim
171 words
A semiconductor memory device comprising a plurality pairs of digit lines connected to a corresponding sense amplifier and one digit line of each pair of digit lines and the other digit line of the same pair interchange their locations on a plane by mutually crossing at least once in a crossing region, one of the digit lines of each pair of digit lines being formed as a first conductor layer and the other digit line of said digit line pair being formed as a second conductor layer formed on said first conductor layer via an insulator film in a region located on one side of said crossing region, said one digit line is formed as the second conductor layer and said other digit line being formed as the first conductor layer in the other region located on the other side of said crossing region, the first conductor layer and the second conductor layer of each digit line being connected in said crossing region via a contact formed in said insulator film.
Claim 7
Dependent Claim
171 words
A semiconductor memory device comprising a plurality pairs of digit lines connected to a corresponding sense amplifier and one digit line of each pair of digit lines and the other digit line of the same pair interchange their locations on a plane by mutually crossing at least once in a crossing region, one of the digit lines of each pair of digit lines being formed as a first conductor layer and the other digit line of said digit line pair being formed as a second conductor layer formed on said first conductor layer via an insulator film in a region located on one side of said crossing region, said one digit line is formed as the second conductor layer and said other digit line being formed as the first conductor layer in the other region located on the other side of said crossing region, the first conductor layer and the second conductor layer of each digit line being connected in said crossing region via a contact formed in said insulator film.
References Cited (Backward Citations)
US4980860A
Cited
US4916661A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-15 | 1995-01-14 | 1995-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-15 | 1999-01-14 | 1999-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-15 | 2003-01-14 | 2003-07-16 | $7700.00 | Window Closed / Lapsed |