US5578847A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic semiconductor memory device with higher density bit line/word line layout
Assignee: Toshiba Corp
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Filing: 1995-03-13
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Granted: 1996-11-26
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Expires: 2015-03-13
Abstract
Abstract A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.
Inventors
- 👤 Masami Aoki
- 👤 Takashi Yamada
- 👤 Hiroshi Takato
- 👤 Tohru Ozaki
- 👤 Katsuhiko Hieda
- 👤 Akihiro Nitayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:22
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; G; G11; G11C; G11C7/00; G11C7/18; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/48; H10B12/482; H10D; H10D89/00; H10D89/10; Y; Y10; Y10S; Y10S257/00; Y10S257/907
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
366 words
A dynamic semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells, each comprising a MOS transistor having a channel region formed in said semiconductor substrate, and a capacitor formed on said semiconductor substrate and having a storage node contact; a plurality of word lines formed on said semiconductor substrate which are formed over said channel regions; a plurality of bit lines formed on said semiconductor substrate to intersect said word lines; a plurality of bit line contacts formed under said bit lines with each commonly used by two memory cells of said memory cells and for electrically connecting each of said bit lines to at least one of said memory cells, wherein first, second and third adjacent word lines are formed so as to have spaces therebetween at a first given pitch, first and second adjacent bit lines are formed so as to intersect said first, second and third adjacent word lines, a first bit line contact is formed in the space between said first and second adjacent word lines under said first bit line, and no bit line contact is formed in the space between said second and third adjacent word lines under said first bit line, a second bit line contact is formed in the space between said second and third adjacent word lines under said second bit line, and no bit line contact is formed in the space between said first and second adjacent word lines under said second bit line, said storage node contact of one of said two memory cells connected to said first bit line contact and said storage node contact of one of said two memory cells connected to a third bit line contact, which is formed under the same bit line as said first bit line contact and is adjacent thereto, are arranged across the bit line, and said storage node contacts of said memory cells, which are connected to adjacent of said bit line contacts connected to the same bit line and which are connected to adjacent of said word lines, are arranged to sandwich the same bit line, and are arranged at the same space between an adjacent two of said word lines.
Claim 2
Dependent Claim
366 words
A dynamic semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells, each comprising a MOS transistor having a channel region formed in said semiconductor substrate, and a capacitor formed on said semiconductor substrate and having a storage node contact; a plurality of word lines formed on said semiconductor substrate which are formed over said channel regions; a plurality of bit lines formed on said semiconductor substrate to intersect said word lines; a plurality of bit line contacts formed under said bit lines with each commonly used by two memory cells of said memory cells and for electrically connecting each of said bit lines to at least one of said memory cells, wherein first, second and third adjacent word lines are formed so as to have spaces therebetween at a first given pitch, first and second adjacent bit lines are formed so as to intersect said first, second and third adjacent word lines, a first bit line contact is formed in the space between said first and second adjacent word lines under said first bit line, and no bit line contact is formed in the space between said second and third adjacent word lines under said first bit line, a second bit line contact is formed in the space between said second and third adjacent word lines under said second bit line, and no bit line contact is formed in the space between said first and second adjacent word lines under said second bit line, said storage node contact of one of said two memory cells connected to said first bit line contact and said storage node contact of one of said two memory cells connected to a third bit line contact, which is formed under the same bit line as said first bit line contact and is adjacent thereto, are arranged across the bit line, and said storage node contacts of said memory cells, which are connected to adjacent of said bit line contacts connected to the same bit line and which are connected to adjacent of said word lines, are arranged to sandwich the same bit line, and are arranged at the same space between an adjacent two of said word lines.
Claim 3
Dependent Claim
22 words
The dynamic semiconductor memory device according to claim 1, wherein said bit lines and word lines are respectively separated at predetermined pitches.
Claim 4
Dependent Claim
21 words
The dynamic semiconductor memory device according to claim 1, wherein said bit lines and said word lines perpendicularly intersect each other.
Claim 5
Dependent Claim
28 words
The dynamic semiconductor memory device according to claim 1, wherein the space between the two adjacent bit lines is larger than the space between two adjacent word lines.
Claim 6
Dependent Claim
27 words
The dynamic semiconductor memory device according to claim 4, wherein the space between the two adjacent bit lines is 1.5 times the space between adjacent word lines.
Claim 7
Dependent Claim
277 words
A dynamic semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells each formed of a MOS transistor and a capacitor which is formed on said semiconductor substrate and has a storage node contact; a plurality of word lines formed on said semiconductor substrate, spaces being provided between adjacent word lines and including odd-numbered and even-numbered spaces; a plurality of bit lines formed on said semiconductor substrate to intersect said word lines, said bit lines including odd-numbered and even-numbered bit lines; and a plurality of bit line contacts formed under said bit lines with each commonly used by two memory cells of said plurality of memory cells, those of said bit line contacts which electrically connect said even-numbered bit lines to said memory cells being arranged in said even-numbered spaces and those of said bit line contacts which electrically connect said odd-numbered bit lines to said memory cells being arranged in said odd-numbered spaces, wherein said storage node contact of one of said two memory cells connected to a said first bit line contact and said storage node contact of one of said two memory cells connected to a second bit line contact, which is formed under the same bit line as said first bit line contact and is adjacent thereto, are arranged across the bit line, and said storage node contacts of said memory cells, which are connected to adjacent of said bit line contacts connected to the same bit line and which are connected to adjacent of said word lines, are arranged to sandwich the same bit line, and are arranged at the same space between an adjacent two of said word lines.
Claim 8
Dependent Claim
277 words
A dynamic semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells each formed of a MOS transistor and a capacitor which is formed on said semiconductor substrate and has a storage node contact; a plurality of word lines formed on said semiconductor substrate, spaces being provided between adjacent word lines and including odd-numbered and even-numbered spaces; a plurality of bit lines formed on said semiconductor substrate to intersect said word lines, said bit lines including odd-numbered and even-numbered bit lines; and a plurality of bit line contacts formed under said bit lines with each commonly used by two memory cells of said plurality of memory cells, those of said bit line contacts which electrically connect said even-numbered bit lines to said memory cells being arranged in said even-numbered spaces and those of said bit line contacts which electrically connect said odd-numbered bit lines to said memory cells being arranged in said odd-numbered spaces, wherein said storage node contact of one of said two memory cells connected to a said first bit line contact and said storage node contact of one of said two memory cells connected to a second bit line contact, which is formed under the same bit line as said first bit line contact and is adjacent thereto, are arranged across the bit line, and said storage node contacts of said memory cells, which are connected to adjacent of said bit line contacts connected to the same bit line and which are connected to adjacent of said word lines, are arranged to sandwich the same bit line, and are arranged at the same space between an adjacent two of said word lines.
Claim 9
Dependent Claim
22 words
A dynamic semiconductor memory device according to claim 6, wherein said bit lines and word lines are respectively arranged at predetermined spaces.
Claim 10
Dependent Claim
21 words
The dynamic semiconductor memory device according to claim 6, wherein said bit lines and said word lines perpendicularly intersect each other.
Claim 11
Dependent Claim
23 words
The dynamic semiconductor memory device according to claim 6, wherein space between adjacent bit lines is larger than space between adjacent word lines.
Claim 12
Dependent Claim
25 words
The dynamic semiconductor memory device according to claim 9, wherein the space between adjacent bit lines is 1.5 times the space between adjacent word lines.
Claim 13
Dependent Claim
68 words
A dynamic semiconductor memory device according to claim 1, wherein each of said plurality of memory cells is formed in an active region which is electrically separated by an element isolation layer, a pair of said word lines which are electrically independent pass through said active region, and one of said transistors is formed at a cross point of said active region and one of said word lines.
Claim 14
Dependent Claim
41 words
A dynamic semiconductor memory device according to claim 11, wherein one of said bit line contacts and two storage node contacts are formed in said active region, and one of said bit line contacts is arranged by crossing said word lines.
Claim 15
Dependent Claim
68 words
A dynamic semiconductor memory device according to claim 6, wherein each of said plurality of memory cells is formed in an active region which is electrically separated by an element isolation layer, a pair of said word lines which are electrically independent pass through said active region, and one of said transistors is formed at a cross point of said active region and one of said word lines.
Claim 16
Dependent Claim
41 words
A dynamic semiconductor memory device according to claim 13, wherein one of said bit line contacts and two storage node contacts are formed in said active region, and one of said bit line contacts is arranged by crossing said word lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-26 | 2000-05-27 | 2000-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-26 | 2004-05-27 | 2004-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-26 | 2008-05-27 | 2008-11-26 | $7700.00 | Window Closed / Lapsed |