Semiconductor memory device and manufacturing method thereof

Claim 2

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion made of a material different from the material of said word line, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a dielectric therebetween, at least one electrode layer of said capacitor electrostatically shielding said bit line.

Claim 3

The semiconductor memory device in accordance with claim 1, wherein the material of said word line has a lower resistance value than the material of said gate electrode portion.

Claim 4

The semiconductor memory device in accordance with claim 2, wherein the material of said word line comprises aluminum, and the material of said gate electrode portion comprises polysilicon.

Claim 5

The semiconductor memory device in accordance with claim 1, wherein said word line is positioned higher than said gate electrode portion, and said word line and said gate electrode portion are electrically connected by a conductive member.

Claim 6

The semiconductor memory device in accordance with claim 4, wherein said conductive member comprises tungsten or molybdenum formed by a selective CVD method.

Claim 7

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface, wherein a plurality of said word lines are provided on said main surface, and said first and second impurity region are provided between adjacent said word lines.

Claim 8

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface, wherein a plurality of said word lines are provided on said main surface, and said first and second impurity region are provided between adjacent said word lines.

Claim 9

The semiconductor memory device in accordance with claim 6, wherein said gate electrode portion and said bit line extended in parallel.

Claim 10

The semiconductor memory device in accordance with claim 6, wherein a direction from said first impurity region to said second impurity region is in parallel with an extending direction of said word lines.

Claim 11

The semiconductor memory device in accordance with claim 6, wherein an interconnection layer is formed above said word line, and said word line and said interconnection layer are electrically connected with each other.

Claim 12

The semiconductor memory device in accordance with claim 6, wherein said second electrode layer overlaps said bit line.

Claim 13

The semiconductor memory device in accordance with claim 6, wherein said first electrode layer overlaps said bit line.

Claim 14

The semiconductor memory device in accordance with claim 10, wherein said first electrode layer overlaps a portion of said bit line, and a second dielectric is provided between said first electrode layer and said bit line and between said second electrode layer and said bit line.

Claim 15

The semiconductor memory device in accordance with claim 12, wherein said second dielectric comprises a silicon oxide film.

Claim 16

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface, wherein said word line is positioned higher than said gate electrode portion, and said word line and said gate electrode portion are electrically connected by a conductive member.

Claim 17

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface, wherein said word line is positioned higher than said gate electrode portion, and said word line and said gate electrode portion are electrically connected by a conductive member.

Claim 18

The semiconductor memory device in accordance with claim 14, wherein a material of said word line has a lower resistance value than a material of said gate electrode portion.

Claim 19

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, wherein a plurality of said word lines are provided on said main surface, and said first and second impurity regions are provided between adjacent said word lines.

Claim 20

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, wherein a plurality of said word lines are provided on said main surface, and said first and second impurity regions are provided between adjacent said word lines.

Claim 21

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, wherein said word line is positioned higher than said gate electrode portion, and said word line and said gate electrode portion are electrically connected by a conductive member.

Claim 22

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, wherein said word line is positioned higher than said gate electrode portion, and said word line and said gate electrode portion are electrically connected by a conductive member.

Claim 23

The semiconductor memory device in accordance with claim 14, wherein said gate electrode portion and said bit line extend in parallel.

Claim 24

The semiconductor memory device in accordance with claim 14, wherein a direction from said first impurity region to said second impurity region is in parallel with an extending direction of said word line.

Claim 25

The semiconductor memory device in accordance with claim 14, wherein a material of said word line has a lower resistance value than a material of said gate electrode portion.

Claim 26

The semiconductor memory device in accordance with claim 14, wherein an interconnection layer is formed above said word line, and said word line and said interconnection layer are electrically connected with each other.

Claim 27

The semiconductor memory device in accordance with claim 14, wherein said second electrode layer overlaps said bit line.

Claim 28

The semiconductor memory device in accordance with claim 14, wherein said first electrode layer overlaps said bit line.

Claim 29

The semiconductor memory device in accordance with claim 20, wherein said first electrode layer overlaps a portion of said bit line, and a second dielectric is provided between said first electrode layer and said bit line.

Claim 30

The semiconductor memory device in accordance with claim 24, wherein said second dielectric comprises a silicon oxide film.

Claim 31

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion branching laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface, wherein a direction from the first impurity region to the second impurity region is in parallel with an extending direction of said word line.

Claim 32

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion branching laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface, wherein a direction from the first impurity region to the second impurity region is in parallel with an extending direction of said word line.

Claim 33

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion branching laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface, wherein a material of said word line has a lower resistance value than a material of said gate electrode portion.

Claim 34

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion branching laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface, wherein a material of said word line has a lower resistance value than a material of said gate electrode portion.

Claim 35

The semiconductor memory device in accordance with claim 16, wherein said gate electrode portion and said bit line extend in parallel.

Claim 36

The semiconductor memory device in accordance with claim 16, wherein a direction form said first impurity region to said second impurity region is in parallel with an extending direction of said word lines.

Claim 37

The semiconductor memory device in accordance with claim 23, wherein a material of said word line has a lower resistance value than a material of said gate electrode portion.

Claim 38

The semiconductor memory device in accordance with claim 15, wherein an interconnection layer is formed above said word line, and said word line and said interconnection layer are electrically connected with each other.

Claim 39

The semiconductor memory device in accordance with claim 16, wherein said second electrode layer overlaps said bit line.

Claim 40

The semiconductor memory device in accordance with claim 16, wherein said first electrode layer overlaps said bit line.

Claim 41

The semiconductor memory device in accordance with claim 32, wherein said first electrode layer overlaps a portion of said bit line, and a second dielectric is provided between said first electrode layer and said bit line.

Claim 42

The semiconductor memory device in accordance with claim 34, wherein said second dielectric comprises a silicon oxide film.

Claim 43

The semiconductor memory device in accordance with claim 17, wherein said gate electrode portion and said bit line extend in parallel.

Claim 44

The semiconductor memory device in accordance with claim 17, wherein a direction from said first impurity region to said second impurity region is in parallel with an extending direction of said word line.

Claim 45

The semiconductor memory device in accordance with claim 17, wherein a material of said word line has a lower resistance value than a material of said gate electrode portion.

Claim 46

The semiconductor memory device in accordance with claim 17, wherein an interconnection layer is formed above said word line, and said word line and said interconnection layer are electrically connected with each other.

Claim 47

The semiconductor memory device in accordance with claim 17, wherein said second electrode layer overlaps said bit line.

Claim 48

The semiconductor memory device in accordance with claim 17, wherein said first electrode layer overlaps said bit line.

Claim 49

The semiconductor memory device in accordance with claim 40, wherein said first electrode layer overlaps a portion of said bit line, and a second dielectric is provided between said first electrode layer and said bit line.

Claim 50

The semiconductor memory device in accordance with claim 42, wherein said second dielectric comprises a silicon oxide film.

Claim 51

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion branching out laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said impurity region, said region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, wherein a direction from said first impurity region to said second impurity region is in parallel with an extending direction of said word line.

Claim 52

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion branching out laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said impurity region, said region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, wherein a direction from said first impurity region to said second impurity region is in parallel with an extending direction of said word line.

Claim 53

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion branching out laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said impurity region, said region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, wherein a material of said word line has a lower resistance value than a material of said gate electrode portion.

Claim 54

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a word line formed on said main surface; a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion branching out laterally from said word line to overlap said channel region; a bit line formed on said main surface to be electrically connected to said impurity region, said region, said bit line crossing said word line at a different level above the substrate; and a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, wherein a material of said word line has a lower resistance value than a material of said gate electrode portion.