US4574465A
Expired / Lapsed
US
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Differing field oxide thicknesses in dynamic memory device
Assignee: Texas Instruments Inc
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Filing: 1982-04-13
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Granted: 1986-03-11
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Expires: 2002-04-13
Abstract
Abstract A dynamic read/write memory device using one-transistor N-channel silicon gate type cells is made by a double-level polysilicon process in which the field oxide is of reduced thickness for the cell array, and of conventional thickness for peripheral circuits. This reduces moat encroachment in the critical cell portion, yet does not force performance compromises in the critical speed paths.
Inventors
- 👤 G. R. Mohan Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:13
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
220 words
A method of making a dynamic semiconductor memory device at a face of a silicon body, including forming an array of one-transistor cells in a cell array area of said face and forming circuits in a peripheral area of said face, comprising the steps of: masking said face of the silicon body to expose first field areas of said cell array area and second field areas of said peripheral area, and to cover transistor and capacitor areas, in the cell array area and peripheral area; implanting channel-stop impurity into both said first and second field areas, growing field oxide to a first thickness in said first and second field areas by exposing said face to an oxidizing atmosphere at high temperature; masking said face with an oxidation mask to expose said second field areas and to cover said first field areas; growing field oxide to a second thickness in said second field areas by exposing said face to an oxidizing atmosphere at high temperature; said field oxide in both said first and second field areas having channel-stop regions beneath the field oxide, said channel-stop regions being of the same conductivity type as said body, thereafter forming polycrystalline silicon electrodes in said transistor and capacitor areas to provide capacitors and transistor gates of memory cells and transistor gates of peripheral transistors.
Claim 2
Independent Claim
220 words
A method of making a dynamic semiconductor memory device at a face of a silicon body, including forming an array of one-transistor cells in a cell array area of said face and forming circuits in a peripheral area of said face, comprising the steps of: masking said face of the silicon body to expose first field areas of said cell array area and second field areas of said peripheral area, and to cover transistor and capacitor areas, in the cell array area and peripheral area; implanting channel-stop impurity into both said first and second field areas, growing field oxide to a first thickness in said first and second field areas by exposing said face to an oxidizing atmosphere at high temperature; masking said face with an oxidation mask to expose said second field areas and to cover said first field areas; growing field oxide to a second thickness in said second field areas by exposing said face to an oxidizing atmosphere at high temperature; said field oxide in both said first and second field areas having channel-stop regions beneath the field oxide, said channel-stop regions being of the same conductivity type as said body, thereafter forming polycrystalline silicon electrodes in said transistor and capacitor areas to provide capacitors and transistor gates of memory cells and transistor gates of peripheral transistors.
Claim 3
Dependent Claim
31 words
A method according to claim 1 wherein the body is P-type silicon, heavily doped N+ regions are formed in said face, and the electrodes include conductive material which is polycrystalline silicon.
Claim 4
Dependent Claim
86 words
A method according to claim 1 wherein the step of forming electrodes includes: applying a first layer of conductive material over said face of the semiconductor body to form a capacitor electrode overlying a first semiconductor region, applying a second layer of conductive material on said face partially overlying the first layer and overlying second and third semiconductor regions, applying a metal layer to said face to define at least one elongated strip overlying the first and second layers and making contact to the second layer.
Claim 5
Dependent Claim
16 words
A method according to claim 2 wherein said masking is by patterned coatings of silicon nitride.
Claim 6
Dependent Claim
20 words
A method according to claim 4 wherein said steps of masking employ separate layers of silicon nitride patterned using photoresist.
Claim 7
Dependent Claim
22 words
A method according to claim 5 wherein said body is annealed in an inert atmosphere before the steps of growing field oxide.
Claim 8
Dependent Claim
28 words
A method according to claim 3 wherein the second layer is patterned to define a conductor segment for connection to the elongated strip which defines an address line.
Claim 9
Dependent Claim
25 words
A method according to claim 7 wherein the first layer is patterned to define a bias gate for the capacitor partially underlying the elongated strip.
Claim 10
Dependent Claim
23 words
A method according to claim 8 wherein a thick insulator separates said layer of metal from said face except at a contact window.
Claim 11
Dependent Claim
42 words
A method according to claim 9 wherein the coating of field oxide of first thickness formed on said face before applying said first conductive layer covers the face only in the memory cell array area, except in the transistor and capacitor areas.
Claim 12
Dependent Claim
36 words
A method according to claim 10 wherein an array of said cells is formed at said face in said array area and the layer of metal includes parallel strips contacting a plurality of cells in columns.
Claim 13
Independent Claim
120 words
A method of making a semiconductor device comprising the steps of: masking a face of a silicon body to expose first and second field areas and cover selected areas; implanting channel-stop impurity in said first and second field areas, said impurity being of the same type as said body, growing thick thermal oxide of a first thickness in said first and second field areas; again masking said face with oxidation-resistant mask to expose only the second field areas; growing thermal oxide of a second thickness in the second field areas; and thereafter forming polycrystalline silicon electrodes in said selected areas to provide circuit elements, at least some of the electrodes being spaced from the thermal oxide in the first area.
Claim 14
Independent Claim
120 words
A method of making a semiconductor device comprising the steps of: masking a face of a silicon body to expose first and second field areas and cover selected areas; implanting channel-stop impurity in said first and second field areas, said impurity being of the same type as said body, growing thick thermal oxide of a first thickness in said first and second field areas; again masking said face with oxidation-resistant mask to expose only the second field areas; growing thermal oxide of a second thickness in the second field areas; and thereafter forming polycrystalline silicon electrodes in said selected areas to provide circuit elements, at least some of the electrodes being spaced from the thermal oxide in the first area.
Claim 15
Dependent Claim
28 words
A method according to claim 12 wherein the silicon body is P type and N type impurity is selectively introduced in said face after said electrodes are formed.
Claim 16
Dependent Claim
17 words
A method according to claim 12 wherein said steps of masking employ silicon nitride patterned using photoresist.
Claim 17
Independent Claim
210 words
A method of making a dynamic semiconductor memory device at a face of a silicon body, including forming an array of one-transistor cells in a cell array area of said face and forming circuits in a peripheral area of said face, wherein first silicon oxide regions are formed in said face in said cell array area to isolate said cells from one another, and wherein second silicon oxide regions are formed in said face in said peripheral area of said face to isolate transistors of said circuits from one another, said method characterized in that said second silicon oxide regions are of a field-oxide thickness substantially greater than a first thickness of said first field oxide regions, and that both said first and said second silicon oxide regions have channel-stop regions beneath the silicon oxide, said channel-stop regions being of the same conductivity-type as said body, comprising the steps of: growing said second field oxide regions to said field-oxide thickness, greater than said first thickness, while said cell array area is masked with an oxidation resistant mask, and after the first and second silicon oxide regions are formed to said thickness, forming polycrystalline silicon electrodes in said cell array area and said peripheral area for said cells and said transistors.
Claim 18
Independent Claim
210 words
A method of making a dynamic semiconductor memory device at a face of a silicon body, including forming an array of one-transistor cells in a cell array area of said face and forming circuits in a peripheral area of said face, wherein first silicon oxide regions are formed in said face in said cell array area to isolate said cells from one another, and wherein second silicon oxide regions are formed in said face in said peripheral area of said face to isolate transistors of said circuits from one another, said method characterized in that said second silicon oxide regions are of a field-oxide thickness substantially greater than a first thickness of said first field oxide regions, and that both said first and said second silicon oxide regions have channel-stop regions beneath the silicon oxide, said channel-stop regions being of the same conductivity-type as said body, comprising the steps of: growing said second field oxide regions to said field-oxide thickness, greater than said first thickness, while said cell array area is masked with an oxidation resistant mask, and after the first and second silicon oxide regions are formed to said thickness, forming polycrystalline silicon electrodes in said cell array area and said peripheral area for said cells and said transistors.
Claim 19
Dependent Claim
22 words
A method according to claim 15 wherein said polycrystalline silicon electrodes include capacitor plates and transistor gates in said cell array area.
Claim 20
Dependent Claim
14 words
A method according to claim 15 wherein said oxidation resistant mask is silicon nitride.
Claim 21
Dependent Claim
22 words
A method according to claim 16 wherein N+ source/drain regions are formed in said faces using said polycrystalline silicon as a mask.
References Cited (Backward Citations)
US4334236A
Cited
US4288910A
Cited
US4326331A
Cited
US4384895A
Cited
US4391032A
Cited
US4335502A
Cited
US4352236A
Cited
US4434543A
Cited
US4435895A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1989-03-10 | 1989-09-09 | 1990-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-10 | 1993-09-09 | 1994-03-11 | $3760.00 | Window Closed / Lapsed |
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