Method and apparatus for source lookup within a central processing unit

Claim 2

A source look-up method comprising the steps of: a) determining a comparison window between an allocation pointer and a deallocation pointer, wherein the allocation pointer points to an entry in a buffer to be allocated next and wherein the deallocation pointer points to an entry in the buffer to be deallocated next; b) for each entry in the buffer between the allocation pointer and the deallocation pointer, comparing a stored value in the each entry with a source value to produce a comparison output; c) flagging each match of the comparison of the stored value in the each entry with the source value to produce flagged matches; and d) identifying, from the flagged matches, an entry having source information of interest based on the allocation pointer.

Claim 3

The method of claim 1, wherein step (a) further comprises the steps of: converting the allocation pointer into an encoded binary allocation value; converting the deallocation pointer into an encoded binary deallocation value; and ORing the encoded binary allocation value and the encoded deallocation value to produce an encoded window.

Claim 4

The method of claim 2 further comprises the steps of: performing a two's complement operation on the allocation pointer to produce the encoded binary allocation value; and performing a two's complement operation on the deallocation pointer to produce the encoded binary deallocation value.

Claim 5

The method of claim 3, wherein the ORing step further comprises: exclusive ORing the encoded binary allocation value and the encoded deallocation value to produce the comparison window.

Claim 6

The method of claim 4, wherein the production of the comparison window further comprises: inverting the comparison window when the allocation pointer wraps around the buffer; and reversing the inversion of the comparison window when the deallocation pointer wraps around the buffer.

Claim 7

The method of claim 2 further comprises: inverting the encoded window to produce an inverted encoded window; and ANDing bits of the inverted encoded window with bits of the comparison output to flag the matches.

Claim 8

The method of claim 6, wherein the identifying, from the flagged matches, an entry having source information of interest based on the allocation pointer further comprises: selecting the entry having source information based on proximity of bit location of the entry having source information within the comparison output to the allocation pointer.

Claim 9

The method of claim 1 further comprises: performing steps (a) through (d) at either dispatch or at execution.

Claim 10

A source look-up circuit comprising: a buffer allocation queue that stores register destination address, register source address, and an buffer allocation entry of instructions that have been allocated an entry in a rename buffer; a buffer allocation memory operably coupled to the buffer allocation queue, wherein the buffer allocation memory stores allocation information pertaining to allocation of a register destination to a rename buffer location in the buffer allocation entry; an allocation pointer circuit operably coupled to the buffer allocation queue and the buffer allocation memory, wherein the allocation pointer circuit provides an allocation pointer; a deallocation pointer register operably coupled to the buffer allocation memory, wherein the deallocation pointer registers stores a deallocation pointer that points to an allocated next entry in the rename buffer to be deallocated; a comparison bank circuit operably coupled to the buffer allocation queue, the buffer allocation memory, the allocation pointer circuit, and the deallocation pointer register, wherein the comparison bank circuit includes: a plurality of comparators, each operably coupled to receive a comparison address and an entry of the buffer allocation memory, the plurality of comparators producing a binary comparison value; determining means, operably coupled to the plurality of comparators, the allocation pointer register, and the deallocation pointer, for determining whether at least one dependent destination address is stored in an entry between the allocation pointer and the deallocation pointer and the at least one dependent destination address has the same address as the comparison address; and selection means, operably coupled to the determining means and the allocation pointer register, for selecting one of the at least one dependent destination addresses as a dependent destination address having information of interest.

Claim 11

A source look-up circuit comprising: a buffer allocation queue that stores register destination address, register source address, and an buffer allocation entry of instructions that have been allocated an entry in a rename buffer; a buffer allocation memory operably coupled to the buffer allocation queue, wherein the buffer allocation memory stores allocation information pertaining to allocation of a register destination to a rename buffer location in the buffer allocation entry; an allocation pointer circuit operably coupled to the buffer allocation queue and the buffer allocation memory, wherein the allocation pointer circuit provides an allocation pointer; a deallocation pointer register operably coupled to the buffer allocation memory, wherein the deallocation pointer registers stores a deallocation pointer that points to an allocated next entry in the rename buffer to be deallocated; a comparison bank circuit operably coupled to the buffer allocation queue, the buffer allocation memory, the allocation pointer circuit, and the deallocation pointer register, wherein the comparison bank circuit includes: a plurality of comparators, each operably coupled to receive a comparison address and an entry of the buffer allocation memory, the plurality of comparators producing a binary comparison value; determining means, operably coupled to the plurality of comparators, the allocation pointer register, and the deallocation pointer, for determining whether at least one dependent destination address is stored in an entry between the allocation pointer and the deallocation pointer and the at least one dependent destination address has the same address as the comparison address; and selection means, operably coupled to the determining means and the allocation pointer register, for selecting one of the at least one dependent destination addresses as a dependent destination address having information of interest.

Claim 12

The source look-up circuit of claim 9 further comprises: a multiplexor operably coupled to the plurality of comparators, wherein the multiplexor receives, as input signals, the register source address and at least one current rename destination address and provides, based on a control signal, either the register source address or one of the at least one current rename source address as the comparison address.

Claim 13

The source look-up circuit of claim 9, wherein the determining means further comprises: means for encoding the allocation pointer to produce an encoded allocation pointer; means for encoding the deallocation pointer to produce an encoded deallocation pointer; a plurality of OR gates for ORing bits of the encoded allocation pointer with bits of the encoded deallocation pointer to produce a binary comparison window; and a plurality of AND gates for ANDing bits of the comparison window with bits of the binary comparison value to identify entries in the buffer allocation memory that are storing the at least one dependent destination address.

Claim 14

The source look-up circuit of claim 11, wherein the determining means further comprises: wrap-around circuit operably coupled to the allocation pointer register, the deallocation pointer register, and the plurality of OR gates, wherein the wrap-around circuit modifies the binary comparison window when the allocation pointer wraps around the buffer allocation memory and unmodifies the binary comparison window when the deallocation pointer wraps-around the buffer allocation memory.

Claim 15

The source look-up circuit of claim 9, wherein the allocation pointer circuit further comprises an allocation pointer register and a multiplexor, wherein the allocation pointer register stores an allocation pointer that points to a next entry for allocation in the rename buffer.

Claim 16

An integrated circuit comprising: data cache; and floating point unit operably coupled to the data cache, wherein the floating point unit includes: floating point register having addressable register locations, wherein an addressable register location is designated as a destination of an executable instruction; pipe assembler operably coupled to the floating point register, the pipe assembler performs at least part of the executable instruction; rename buffer operably coupled to the floating point register, wherein the rename buffer stores, at an allocated buffer location, the addressable register location; a buffer allocation queue that stores the addressable register location, a source address, and the allocated buffer location of the executable instruction; a buffer allocation memory operably coupled to the buffer allocation queue, wherein the buffer allocation memory stores the addressable register location in an entry having a corresponding address as the allocated buffer location; an allocation pointer circuit operably coupled to the buffer allocation queue and the buffer allocation memory, wherein the allocation pointer circuit provides an allocation pointer; a deallocation pointer register operably coupled to the buffer allocation memory, wherein the deallocation pointer registers stores a deallocation pointer that points to an allocated entry in the rename buffer to is to be deallocated next; a comparison bank circuit operably coupled to the buffer allocation queue, the buffer allocation memory, the allocation pointer circuit, and the deallocation pointer register, wherein the comparison bank circuit includes: a plurality of comparators, each operably coupled to receive a comparison address and an entry of the buffer allocation memory, the plurality of comparators producing a binary comparison value; determining means, operably coupled to the plurality of comparators, the allocation pointer register, and the deallocation pointer, for determining whether at least one dependent destination address is stored in an entry between the allocation pointer and the deallocation pointer and the at least one dependent destination address has the same address as the comparison address; and selection means, operably coupled to the determining means and the allocation pointer register, for selecting one of the at least one dependent destination addresses as a dependent destination address having information of interest.

Claim 17

An integrated circuit comprising: data cache; and floating point unit operably coupled to the data cache, wherein the floating point unit includes: floating point register having addressable register locations, wherein an addressable register location is designated as a destination of an executable instruction; pipe assembler operably coupled to the floating point register, the pipe assembler performs at least part of the executable instruction; rename buffer operably coupled to the floating point register, wherein the rename buffer stores, at an allocated buffer location, the addressable register location; a buffer allocation queue that stores the addressable register location, a source address, and the allocated buffer location of the executable instruction; a buffer allocation memory operably coupled to the buffer allocation queue, wherein the buffer allocation memory stores the addressable register location in an entry having a corresponding address as the allocated buffer location; an allocation pointer circuit operably coupled to the buffer allocation queue and the buffer allocation memory, wherein the allocation pointer circuit provides an allocation pointer; a deallocation pointer register operably coupled to the buffer allocation memory, wherein the deallocation pointer registers stores a deallocation pointer that points to an allocated entry in the rename buffer to is to be deallocated next; a comparison bank circuit operably coupled to the buffer allocation queue, the buffer allocation memory, the allocation pointer circuit, and the deallocation pointer register, wherein the comparison bank circuit includes: a plurality of comparators, each operably coupled to receive a comparison address and an entry of the buffer allocation memory, the plurality of comparators producing a binary comparison value; determining means, operably coupled to the plurality of comparators, the allocation pointer register, and the deallocation pointer, for determining whether at least one dependent destination address is stored in an entry between the allocation pointer and the deallocation pointer and the at least one dependent destination address has the same address as the comparison address; and selection means, operably coupled to the determining means and the allocation pointer register, for selecting one of the at least one dependent destination addresses as a dependent destination address having information of interest.

Claim 18

The integrated circuit of claim 14 further comprises: a multiplexor operably coupled to the plurality of comparators, wherein the multiplexor receives, as input signals, the register source address and at least one current rename destination address and provides, based on a control signal, either the register source address or one of the at least one current rename source address as the comparison address.

Claim 19

The integrated circuit of claim 14, wherein the determining means further comprises: means for encoding the allocation pointer to produce an encoded allocation pointer; means for encoding the deallocation pointer to produce an encoded deallocation pointer; a plurality of OR gates for ORing bits of the encoded allocation pointer with bits of the encoded deallocation pointer to produce a binary comparison window; and a plurality of AND gates for ANDing bits of the comparison window with bits of the binary comparison value to identify entries in the buffer allocation memory that are storing the at least one dependent destination address.

Claim 20

The integrated circuit of claim 16, wherein the determining means further comprises: wrap-around circuit operably coupled to the allocation pointer register, the deallocation pointer register, and the plurality of OR gates, wherein the wrap-around circuit modifies the binary comparison window when the allocation pointer wraps around the buffer allocation memory and unmodifies the binary comparison window when the deallocation pointer wraps-around the buffer allocation memory.

Claim 21

The integrated circuit of claim 14, wherein the allocation pointer circuit further comprises an allocation pointer register and a multiplexor, wherein the allocation pointer register stores an allocation pointer that points to a next entry for allocation in the rename buffer.

Claim 22

An integrated circuit comprising: data cache; instruction cache; and fixed point unit operably coupled to the data cache and the instruction cache, wherein the fixed point unit includes: general purpose register having addressable register locations, wherein an addressable register location is designated as a destination of an executable instruction; arithmetic logic unit operably coupled to the fixed point register, the arithmetic logic unit performs at least part of the executable instruction; rename buffer operably coupled to the fixed point register, wherein the rename buffer stores, at an allocated buffer location, the addressable register location; a buffer allocation queue that stores the addressable register location, a source address, and the allocated buffer location of the executable instruction; a buffer allocation memory operably coupled to the buffer allocation queue, wherein the buffer allocation memory stores the addressable register location in an entry having a corresponding address as the allocated buffer location; an allocation pointer circuit operably coupled to the buffer allocation queue and the buffer allocation memory, wherein the allocation pointer circuit provides an allocation pointer; a deallocation pointer register operably coupled to the buffer allocation memory, wherein the deallocation pointer registers stores a deallocation pointer that points to an allocated entry in the rename buffer to is to be deallocated next; a comparison bank circuit operably coupled to the buffer allocation queue, the buffer allocation memory, the allocation pointer circuit, and the deallocation pointer register, wherein the comparison bank circuit includes: a plurality of comparators, each operably coupled to receive a comparison address and an entry of the buffer allocation memory, the plurality of comparators producing a binary comparison value; determining means, operably coupled to the plurality of comparators, the allocation pointer register, and the deallocation pointer, for determining whether at least one dependent destination address is stored in an entry between the allocation pointer and the deallocation pointer and the at least one dependent destination address has the same address as the comparison address; and selection means, operably coupled to the determining means and the allocation pointer register, for selecting one of the at least one dependent destination addresses as a dependent destination address having information of interest.

Claim 23

An integrated circuit comprising: data cache; instruction cache; and fixed point unit operably coupled to the data cache and the instruction cache, wherein the fixed point unit includes: general purpose register having addressable register locations, wherein an addressable register location is designated as a destination of an executable instruction; arithmetic logic unit operably coupled to the fixed point register, the arithmetic logic unit performs at least part of the executable instruction; rename buffer operably coupled to the fixed point register, wherein the rename buffer stores, at an allocated buffer location, the addressable register location; a buffer allocation queue that stores the addressable register location, a source address, and the allocated buffer location of the executable instruction; a buffer allocation memory operably coupled to the buffer allocation queue, wherein the buffer allocation memory stores the addressable register location in an entry having a corresponding address as the allocated buffer location; an allocation pointer circuit operably coupled to the buffer allocation queue and the buffer allocation memory, wherein the allocation pointer circuit provides an allocation pointer; a deallocation pointer register operably coupled to the buffer allocation memory, wherein the deallocation pointer registers stores a deallocation pointer that points to an allocated entry in the rename buffer to is to be deallocated next; a comparison bank circuit operably coupled to the buffer allocation queue, the buffer allocation memory, the allocation pointer circuit, and the deallocation pointer register, wherein the comparison bank circuit includes: a plurality of comparators, each operably coupled to receive a comparison address and an entry of the buffer allocation memory, the plurality of comparators producing a binary comparison value; determining means, operably coupled to the plurality of comparators, the allocation pointer register, and the deallocation pointer, for determining whether at least one dependent destination address is stored in an entry between the allocation pointer and the deallocation pointer and the at least one dependent destination address has the same address as the comparison address; and selection means, operably coupled to the determining means and the allocation pointer register, for selecting one of the at least one dependent destination addresses as a dependent destination address having information of interest.