US5584037A
Expired / Lapsed
US
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Entry allocation in a circular buffer
Assignee: Intel Corp
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Filing: 1995-12-13
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Granted: 1996-12-10
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Expires: 2015-12-13
Abstract
Abstract An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.
Inventors
- 👤 David B. Papworth
- 👤 Andrew F. Glew
- 👤 Michael A. Fetterman
- 👤 Glenn J. Hinton
- 👤 Robert P. Colwell
- 👤 Steven J. Griffith
- 👤 Shantanu R. Gupta
- 👤 Narayan Hegde
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:52
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F5/12; G06F5/14; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3842; G06F9/3844; G06F9/3854; G06F9/3856; G06F9/3858; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
142 words
A method for determining relative age of a plurality of instructions stored in a circular buffer in a microprocessor capable of performing out-of-order dispatch and execution of said plurality of instructions, said method comprising the steps of: assigning a physical destination (Pdst), inducting a wrap bit, for each of said plurality of instructions, wherein said Pdst for each instruction corresponds to an original program order for said plurality of instructions, and said wrap bit indicating whether assignment of Pdsts traversed a linear queue of said circular buffer; comparing said Pdsts and said wrap bits of a first instruction and a second instruction for relative age determination; designating said instruction comprising the smallest Pdst as said oldest instruction when said wrap bits are equal; and designating said instruction comprising the largest Pdst as said oldest instruction when said wrap bits are not equal.
Claim 2
Independent Claim
142 words
A method for determining relative age of a plurality of instructions stored in a circular buffer in a microprocessor capable of performing out-of-order dispatch and execution of said plurality of instructions, said method comprising the steps of: assigning a physical destination (Pdst), inducting a wrap bit, for each of said plurality of instructions, wherein said Pdst for each instruction corresponds to an original program order for said plurality of instructions, and said wrap bit indicating whether assignment of Pdsts traversed a linear queue of said circular buffer; comparing said Pdsts and said wrap bits of a first instruction and a second instruction for relative age determination; designating said instruction comprising the smallest Pdst as said oldest instruction when said wrap bits are equal; and designating said instruction comprising the largest Pdst as said oldest instruction when said wrap bits are not equal.
Claim 3
Independent Claim
153 words
An apparatus for determining relative age of a plurality of instructions stored in a circular buffer in a microprocessor capable of performing out-of-order dispatch and execution of said plurality of instructions, said apparatus comprising: an allocation circuit for assigning a physical destination (Pdst), including a wrap bit, for each of said plurality of instructions, wherein said Pdst for each instruction corresponds to an original program order for said plurality of instructions, and said wrap bit indicates whether assignment of Pdsts traversed a linear queue of said circular buffer; a comparator circuit for comparing said Pdsts and said wrap bits of a first instruction and a second instruction for relative age determination; and a selection circuit for designating said instruction comprising the smallest Pdst as said oldest instruction when said wrap bits are equal, and for designating said instruction comprising the largest Pdst as said oldest instruction when said wrap bits are not equal.
Claim 4
Independent Claim
153 words
An apparatus for determining relative age of a plurality of instructions stored in a circular buffer in a microprocessor capable of performing out-of-order dispatch and execution of said plurality of instructions, said apparatus comprising: an allocation circuit for assigning a physical destination (Pdst), including a wrap bit, for each of said plurality of instructions, wherein said Pdst for each instruction corresponds to an original program order for said plurality of instructions, and said wrap bit indicates whether assignment of Pdsts traversed a linear queue of said circular buffer; a comparator circuit for comparing said Pdsts and said wrap bits of a first instruction and a second instruction for relative age determination; and a selection circuit for designating said instruction comprising the smallest Pdst as said oldest instruction when said wrap bits are equal, and for designating said instruction comprising the largest Pdst as said oldest instruction when said wrap bits are not equal.
Claim 5
Dependent Claim
304 words
A microprocessor comprising: an instruction fetch circuit for fetching instructions and predicting branch instructions and corresponding target addresses for said predicted branch instructions; an instruction decoder for decoding and issuing said instructions fetched in an original program order; an execution cluster comprising at least on execution unit for executing said instructions; out-of-order dispatch logic for dispatching said instructions issued to said execution units in said execution cluster based on data dependencies and execution unit availability, said out-of-order dispatch logic being constructed to reorder said instructions in said original program order upon completion of execution; a reorder buffer coupled to said out-of-order dispatch logic for storing data, corresponding to said instructions issued; an allocation circuit coupled to said instruction decoder for receiving instructions, coupled to said branch execution unit, and coupled to said reorder buffer for assigning a physical destination (Pdst), including a wrap bit, for each of said plurality of instructions, wherein said Pdst for each instruction corresponds to said original program order for said plurality of instructions, and said wrap bit indicates whether assignment of Pdsts traversed a linear queue of said reorder buffer; and a branch execution unit for calculating an outcome for said predicted branches, said branch execution unit comprising: a comparator circuit for comparing said Pdsts and said wrap bits of a first mispredicted branch instruction and a second mispredicted branch instruction for relative age determination; a selection circuit for designating said instruction comprising the smallest Pdst as said oldest instruction when said wrap bits are equal, and for designating said instruction comprising the largest Pdst as said oldest instruction when said wrap bits are not equal; and a flushing circuit for clearing said instructions fetched but not issued, said flushing circuit being constructed to clear said instructions fetched but not issued when said oldest branch instruction has been mispredicted.
Claim 6
Dependent Claim
304 words
A microprocessor comprising: an instruction fetch circuit for fetching instructions and predicting branch instructions and corresponding target addresses for said predicted branch instructions; an instruction decoder for decoding and issuing said instructions fetched in an original program order; an execution cluster comprising at least on execution unit for executing said instructions; out-of-order dispatch logic for dispatching said instructions issued to said execution units in said execution cluster based on data dependencies and execution unit availability, said out-of-order dispatch logic being constructed to reorder said instructions in said original program order upon completion of execution; a reorder buffer coupled to said out-of-order dispatch logic for storing data, corresponding to said instructions issued; an allocation circuit coupled to said instruction decoder for receiving instructions, coupled to said branch execution unit, and coupled to said reorder buffer for assigning a physical destination (Pdst), including a wrap bit, for each of said plurality of instructions, wherein said Pdst for each instruction corresponds to said original program order for said plurality of instructions, and said wrap bit indicates whether assignment of Pdsts traversed a linear queue of said reorder buffer; and a branch execution unit for calculating an outcome for said predicted branches, said branch execution unit comprising: a comparator circuit for comparing said Pdsts and said wrap bits of a first mispredicted branch instruction and a second mispredicted branch instruction for relative age determination; a selection circuit for designating said instruction comprising the smallest Pdst as said oldest instruction when said wrap bits are equal, and for designating said instruction comprising the largest Pdst as said oldest instruction when said wrap bits are not equal; and a flushing circuit for clearing said instructions fetched but not issued, said flushing circuit being constructed to clear said instructions fetched but not issued when said oldest branch instruction has been mispredicted.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |