US5739587A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having a multi-latered wiring structure
Assignee: Seiko Epson Corp
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Filing: 1996-02-20
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Granted: 1998-04-14
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Expires: 2016-02-20
Abstract
Abstract The present invention relates to a pad for connecting external connection terminals such as bonding wires to IC chip. The present invention provides a semiconductor device having upper and lower electrode layers and an interlayer insulation film therebetween, the interlayer insulation film including a through hole which is formed therethrough at a given location. An interlayer connection conductor is embedded in the through hole. For example, the ball-like portion of the bonding wire may be connected to the upper electrode layer such that the ball-like portion perfectly covers the embedded conductor. Such an arrangement will not create any step. Therefore, the bonding area can be easily ensured to facilitate a further formation of more layers. The embedded metal will not be adversely affected by moisture moved into along the bonding wire. The external connection terminal may be of any suitable form such as bump electrode and film carrier. The present invention may be broadly applied as a connection technique for these terminals. It is particularly important to secure a desired bonding area and to provide any measure against larger pressing and separating forces if the connection is made using the bonding wire. In view of improvement of the reliability, the present invention is effective. The through holes may be replaced by grooves into each of which an interlayer connection conductor is embedded. If the plane configuration in the grooves is modified, moisture can be more effectively prevented from entering the semiconductor device through the outer periphery of the IC chip.
Inventors
- 👤 Hisakatsu Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:15
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/01; H10W72/019; H10W72/50; H10W72/531; H10W72/536; H10W72/541; H10W72/5449; H10W72/551; H10W72/552; H10W72/5524; H10W72/59; H10W72/90; H10W72/921; H10W72/923; H10W72/9232; H10W72/931; H10W72/932; H10W72/934; H10W72/951; H10W72/952; H10W72/981; H10W72/983
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
120 words
A semiconductor device having a multi-layered wiring structure comprising: a first conductor layer connected to an external connection terminal; a second conductor layer; an electrical insulation layer interposed between said first and second conductor layers; and a third conductor layer embedded in a through hole selectively formed through said electrical insulation layer, said third conductor layer electrically connecting said first conductor layer to said second conductor layer; wherein said third conductor layer is filled in said through hole, the height of the top and bottom of said third conductor layer being substantially equal to the height of the top and bottom of said electrical insulation layer and said third conductor layer is harder than said first and second conductor layers.
Claim 2
Dependent Claim
120 words
A semiconductor device having a multi-layered wiring structure comprising: a first conductor layer connected to an external connection terminal; a second conductor layer; an electrical insulation layer interposed between said first and second conductor layers; and a third conductor layer embedded in a through hole selectively formed through said electrical insulation layer, said third conductor layer electrically connecting said first conductor layer to said second conductor layer; wherein said third conductor layer is filled in said through hole, the height of the top and bottom of said third conductor layer being substantially equal to the height of the top and bottom of said electrical insulation layer and said third conductor layer is harder than said first and second conductor layers.
Claim 3
Dependent Claim
28 words
The semiconductor device as defined in claim 1 wherein a surface of said third conductor layer contacting said first conductor layer is covered with said external connection terminal.
Claim 4
Dependent Claim
33 words
The semiconductor device as defined in claim 1 wherein said first and second conductor layers contain aluminum as a chief component and wherein said third conductor layer contains tungsten as a chief component.
Claim 5
Dependent Claim
51 words
The semiconductor device as defined in claim 1, further comprising an internal circuit formed by a multi-layered wiring structure and wherein said first, second and third conductor layers, electrical insulation layer and through hole are formed through the same production process as forming said multi-layered wiring structure of said internal circuit.
Claim 6
Dependent Claim
17 words
The semiconductor device as defined in claim 1 wherein said external connection terminal is a bonding wire.
Claim 7
Dependent Claim
154 words
A semiconductor device having a multi-layered wiring structure comprising: a first conductor layer connected to an external connection terminal; a second conductor layer; an electrical insulation layer interposed between said first and second conductor layers; and a plurality of third conductor layers each embedded in one of a plurality of through holes selectively formed through said electrical insulation layer, said third conductor layers electrically connecting said first conductor layer to said second conductor layer; wherein each of said third conductor layers is filled in the corresponding one of said through holes, the height of the top and bottom of the third conductor layer being substantially equal to the height of the top and bottom of said electrical insulation layer and said third conductor layers are arranged into a matrix; and wherein a surface of at least one of said third conductor layers contacting said first conductor layer is covered with said external connection terminal.
Claim 8
Dependent Claim
154 words
A semiconductor device having a multi-layered wiring structure comprising: a first conductor layer connected to an external connection terminal; a second conductor layer; an electrical insulation layer interposed between said first and second conductor layers; and a plurality of third conductor layers each embedded in one of a plurality of through holes selectively formed through said electrical insulation layer, said third conductor layers electrically connecting said first conductor layer to said second conductor layer; wherein each of said third conductor layers is filled in the corresponding one of said through holes, the height of the top and bottom of the third conductor layer being substantially equal to the height of the top and bottom of said electrical insulation layer and said third conductor layers are arranged into a matrix; and wherein a surface of at least one of said third conductor layers contacting said first conductor layer is covered with said external connection terminal.
Claim 9
Dependent Claim
45 words
The semiconductor device is defined in claim 6 wherein said third conductor layers are arranged into a plurality of lines forming a matrix of even number lines and odd number lines, the even number lines being staggered from the odd number lines in said matrix.
Claim 10
Dependent Claim
18 words
The semiconductor device as defined in claim 6 wherein said third conductor layers are arranged into concentric circles.
Claim 11
Dependent Claim
104 words
A semiconductor device having a multi-layered wiring structure comprising: a first conductor layer connected to an external connection terminal; a second conductor layer; an electrical insulation layer interposed between said first and second conductor layers; and a third conductor layer embedded into a groove selectively formed in said electrical insulation layer, said third conductor layer electrically connecting said first conductor layer to said second conductor layer; wherein said third conductor layer is filled in said groove, the height of the top and bottom of said third conductor layer being substantially equal to the height of the top and bottom of said electrical insulation layer.
Claim 12
Dependent Claim
104 words
A semiconductor device having a multi-layered wiring structure comprising: a first conductor layer connected to an external connection terminal; a second conductor layer; an electrical insulation layer interposed between said first and second conductor layers; and a third conductor layer embedded into a groove selectively formed in said electrical insulation layer, said third conductor layer electrically connecting said first conductor layer to said second conductor layer; wherein said third conductor layer is filled in said groove, the height of the top and bottom of said third conductor layer being substantially equal to the height of the top and bottom of said electrical insulation layer.
Claim 13
Dependent Claim
95 words
The semiconductor device as defined in claim 9, wherein said third conductor layer embedded into said groove is formed into a closed configuration, said electrical insulation layer being partitioned into inner and outer portions about said closed configuration; wherein said inner portion of said electrical insulation layer includes a through hole selectively formed therethrough, said through hole including a fourth conductor layer embedded thereinto and formed of the same material as in said third conductor layer; and wherein said external connection terminal is connected to said first conductor layer to cover said fourth conductor layer.
Claim 14
Dependent Claim
272 words
A semiconductor device having a multi-layered wiring structure comprising: a first conductor layer connected to an external connection terminal; a second conductor layer; a third conductor layer formed to have an overlap relative to said second conductor layer; a first electrical insulation layer interposed between said first and second conductor layers; a second electrical insulation layer interposed between said second and third conductor layers; a fourth conductor layer embedded into a first through hole selectively formed through said first electrical insulation layer, said fourth conductor layer electrically connecting said first conductor layer to said second conductor layer; and a fifth conductor layer embedded into a second through hole selectively formed through said second electrical insulation layer, said fifth conductor layer electrically connecting said second conductor layer to said third conductor layer; a guard ring located at a position nearer an outer periphery of the semiconductor device than the position at which said external connection terminal is connected to the semiconductor device, said guard ring having a given potential; wherein said fourth conductor layer is filled in said first through hole such that the height of the top and bottom of said fourth conductor layer is substantially equal to the height of the top and bottom of said first electrical insulation layer; wherein said fifth conductor layer is filled in said second through hole such that the height of the top and bottom of said fifth conductor layer is substantially equal to the height of the top and bottom of said second electrical insulation layer; and wherein said fourth and fifth conductor layers in said first and second through holes have an overlap.
Claim 15
Dependent Claim
272 words
A semiconductor device having a multi-layered wiring structure comprising: a first conductor layer connected to an external connection terminal; a second conductor layer; a third conductor layer formed to have an overlap relative to said second conductor layer; a first electrical insulation layer interposed between said first and second conductor layers; a second electrical insulation layer interposed between said second and third conductor layers; a fourth conductor layer embedded into a first through hole selectively formed through said first electrical insulation layer, said fourth conductor layer electrically connecting said first conductor layer to said second conductor layer; and a fifth conductor layer embedded into a second through hole selectively formed through said second electrical insulation layer, said fifth conductor layer electrically connecting said second conductor layer to said third conductor layer; a guard ring located at a position nearer an outer periphery of the semiconductor device than the position at which said external connection terminal is connected to the semiconductor device, said guard ring having a given potential; wherein said fourth conductor layer is filled in said first through hole such that the height of the top and bottom of said fourth conductor layer is substantially equal to the height of the top and bottom of said first electrical insulation layer; wherein said fifth conductor layer is filled in said second through hole such that the height of the top and bottom of said fifth conductor layer is substantially equal to the height of the top and bottom of said second electrical insulation layer; and wherein said fourth and fifth conductor layers in said first and second through holes have an overlap.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-13 | 2001-10-13 | 2002-04-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-13 | 2005-10-13 | 2006-04-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-13 | 2009-10-13 | 2010-04-14 | $7700.00 | Window Closed / Lapsed |