US5621247A
Expired / Lapsed
US
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Memory device with tungsten and aluminum interconnects
Assignee: Panasonic Holdings Corp
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Filing: 1996-02-16
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Granted: 1997-04-15
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Expires: 2016-02-16
Abstract
Abstract On an insulating substrate are formed first aluminum interconnections. In openings formed in a silicon dioxide film are formed unit cells each consisting of a tungsten electrode and an aluminum alloy electrode containing silicon. Over the silicon dioxide film are formed a large number of linear second aluminum interconnections which are orthogonal to the first aluminum interconnections. At the individual intersections of the first and second aluminum interconnections are disposed the unit cells so as to compose a memory cell array. When a large current is allowed to flow through the unit cell, silicon in the aluminum alloy electrode moves in a direction opposite to the current flow and is precipitated in the aluminum electrode in the vicinity of the interface with the tungsten electrode, resulting in an increase in resistance value. When a large current is allowed to flow through the unit cell in the opposite direction, silicon is diffused, resulting in a reduction in resistance value. Data can be read by measuring the magnitude of the resistance value with an extremely small current and judging whether it is in a high state or in a low state.
Inventors
- 👤 Shuji Hirao
- 👤 Hideko Okada
- 👤 Kousaku Yano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:49
CPC Classifications
G; G11; G11C; G11C13/00; H; H10; H10W; H10W20/00; H10W20/01; G11C13/0002; G11C13/0021; G11C13/0069; G11C17/00; G11C17/08; G11C17/10; H10B; H10B63/00; H10B63/30; H10B63/80; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10N; H10N70/00; H10N70/011; H10N70/021; H10N70/023; H10N70/061; H10N70/066; H10N70/20; H10N70/24; H10N70/245; H10N70/801; H10N70/821; H10N70/826; H10N70/828; H10N70/881; G11C2013/0073; G11C2213/00; G11C2213/30; G11C2213/33; G11C2213/50; G11C2213/56; G11C2213/70; G11C2213/77
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
148 words
A memory device comprising: a first conductive member; a second conductive member provided to be opposed to said first conductive member; and a resistance varying member interposed between said first conductive member and said second conductive member, said resistance varying member having a resistance varying characteristic such that its resistance varies due to a movement of atoms which occurs when a current equal to or higher than a specified value is allowed to flow therethrough and a function of retaining a high-resistance state and a low-resistance state as data, wherein said data can be written in said resistance varying member by allowing a first current equal to or higher than said specified value to flow through said resistance varying member and said data can be read from said resistance varying member by allowing a second current lower than said specified value to flow through said resistance varying member.
Claim 2
Dependent Claim
148 words
A memory device comprising: a first conductive member; a second conductive member provided to be opposed to said first conductive member; and a resistance varying member interposed between said first conductive member and said second conductive member, said resistance varying member having a resistance varying characteristic such that its resistance varies due to a movement of atoms which occurs when a current equal to or higher than a specified value is allowed to flow therethrough and a function of retaining a high-resistance state and a low-resistance state as data, wherein said data can be written in said resistance varying member by allowing a first current equal to or higher than said specified value to flow through said resistance varying member and said data can be read from said resistance varying member by allowing a second current lower than said specified value to flow through said resistance varying member.
Claim 3
Dependent Claim
66 words
A memory device according to claim 1, wherein said resistance varying member is composed of a material having the resistance varying characteristic such that its resistance varies as a result of the formation of a void in the vicinity of an end portion thereof due to the movement of the constituent atoms which is caused by the current equal to or higher than said specified value.
Claim 4
Dependent Claim
18 words
A memory device according to claim 2, wherein said resistance varying member is composed of substantially pure aluminum.
Claim 5
Dependent Claim
66 words
A memory device according to claim 3, wherein said first conductive member and said second conductive member are stacked in layers via an interlayer insulating film, said interlayer insulating film is formed with an opening connecting said first and second conductive members with each other, and said resistance varying member is an aluminum electrode stacked in layers in conjunction with a tungsten electrode in said opening.
Claim 6
Dependent Claim
36 words
A memory device according to claim 4, wherein a contact area between said aluminum electrode and said tungsten electrode is smaller than a contact area between said aluminum electrode and said first or second conductive member.
Claim 7
Dependent Claim
74 words
A memory device according to claim 1, wherein said data written in said resistance varying member can be erased therefrom by switching the high-resistance or low-resistance state of said resistance varying member to the opposite state by allowing a third current equal to or higher than said specified value to flow in a direction opposite to the flow of said first current through said resistance varying member via said first and second conductive members.
Claim 8
Dependent Claim
57 words
A memory device according to claim 6, wherein said resistance varying member is composed of a main material and an impurity and has the resistance varying characteristic such that its resistance varies due to the movement of the impurity in said main material which is caused by the current equal to or higher than said specified value.
Claim 9
Dependent Claim
25 words
A memory device according to claim 7, wherein said main material is aluminum and said aluminum contains 0.5% to 20% of silicon as said impurity.
Claim 10
Dependent Claim
67 words
A memory device according to claim 8, wherein said first conductive member and said second conductive member are stacked in layers via an interlayer insulating film, said interlayer insulating film is formed with an opening connecting said first and second conductive members with each other, and said resistance varying member is an aluminum alloy electrode stacked in layers in conjunction with a tungsten electrode in said opening.
Claim 11
Dependent Claim
38 words
A memory device according to claim 9, wherein a contact area between said aluminum alloy electrode and said tungsten electrode is smaller than a contact area between said aluminum alloy electrode and said first or second conductive member.
Claim 12
Dependent Claim
68 words
A memory device according to claim 1, wherein said first conductive member is composed of a plurality of first interconnections extending in parallel to each other, said second conductive member is composed of a plurality of second interconnections extending in a direction orthogonal to said respective first interconnections, and said resistance varying member is disposed at each of the intersections of said first interconnections and said second interconnections.
Claim 13
Dependent Claim
133 words
A memory device according to claim 11, further comprising: a plurality of MOS transistors each consisting of a semiconductor substrate, a gate electrode, a source region, and a drain region; and a plurality of bit lines connected to the source regions of said respective MOS transistors, wherein said first conductive members are impurity diffusion layers formed by introducing an impurity into a plurality of linear regions of said semiconductor substrate, which has been partitioned by a plurality of isolating insulating films, and having their surfaces silicidized, said first conductive members are connected to the drain regions of said respective MOS transistors, and data can be written and read in and from that one of the resistance varying members selected via said gate electrode and said bit line of each of said MOS transistors.
Claim 14
Dependent Claim
111 words
A memory device according to claim 12, wherein said data written in said resistance varying member can be erased therefrom by switching the high-resistance or low-resistance state of said resistance varying member to the opposite state by allowing a third current equal to or higher than said specified value to flow in a direction opposite to the flow of said first current through said resistance varying member via said first and second conductive members and the data can be erased from the resistance varying member which has been selected via said gate electrode and said bit line of each of said MOS transistors and in which the data has been written.
Claim 15
Dependent Claim
115 words
A memory device according to claim 11, further comprising: a plurality of MOS transistors each consisting of a semiconductor substrate, a gate electrode, a source region, and a drain region; and a plurality of bit lines connected to the source regions of said respective MOS transistors, wherein said first conductive members are formed over said respective MOS transistors via insulating films, said resistance varying members are connected to the drain regions of said respective MOS transistors via contacts formed in said insulating films, and data can be written and read in and from that one of the resistance varying members selected via said gate electrode and said bit line of each of said MOS transistors.
Claim 16
Dependent Claim
111 words
A memory device according to claim 14, wherein said data written in said resistance varying member can be erased therefrom by switching the high-resistance or low-resistance state of said resistance varying member to the opposite state by allowing a third current equal to or higher than said specified value to flow in a direction opposite to the flow of said first current through said resistance varying member via said first and second conductive members and the data can be erased from the resistance varying member which has been selected via said gate electrode and said bit line of each of said MOS transistors and in which the data has been written.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-14 | 2000-10-14 | 2001-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-14 | 2004-10-14 | 2005-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-14 | 2008-10-14 | 2009-04-15 | $7700.00 | Window Closed / Lapsed |