US5736456A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming conductive bumps on die for flip chip applications
Assignee: Micron Technology Inc
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Filing: 1996-07-17
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Granted: 1998-04-07
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Expires: 2016-07-17
Abstract
Abstract The present invention relates to an improved method for forming a UBM pads and solder bump connections for flip chip which eliminates at least one mask step required in standard UBM pad forming processes. The method also includes repatterning bond pad locations.
Inventors
- 👤 Salman Akram
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:06
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/01; H10W72/012; H10W72/019; H10W72/20; H10W70/00; H10W70/01; H10W70/05; H10W72/01251; H10W72/01255; H10W72/241; H10W72/242; H10W72/251; H10W72/252; H10W72/29; H10W72/90; H10W72/921; H10W72/923; H10W72/931; H10W72/934; H10W72/941; H10W72/9415; H10W72/942; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10S; Y10S438/00; Y10S438/959
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
123 words
A method of fabricating under bump metallization on a semiconductor substrate, comprising: providing a semiconductor substrate including integrated circuitry on at least one surface thereof, and at least one passivation layer having a thickness and disposed thereover; providing access to said semiconductor integrated circuitry for external contact by forming at least one via extending through said at least one passivation layer; forming a substantially conformal metal layer of a thickness substantially less than the passivation layer thickness over said at least one passivation layer with a portion of said metal layer extending into said at least one via to made electrical contact with said semiconductor integrated circuitry; and removing said metal layer only above said at least one passivation layer by abrasive contact.
Claim 2
Independent Claim
123 words
A method of fabricating under bump metallization on a semiconductor substrate, comprising: providing a semiconductor substrate including integrated circuitry on at least one surface thereof, and at least one passivation layer having a thickness and disposed thereover; providing access to said semiconductor integrated circuitry for external contact by forming at least one via extending through said at least one passivation layer; forming a substantially conformal metal layer of a thickness substantially less than the passivation layer thickness over said at least one passivation layer with a portion of said metal layer extending into said at least one via to made electrical contact with said semiconductor integrated circuitry; and removing said metal layer only above said at least one passivation layer by abrasive contact.
Claim 3
Dependent Claim
13 words
The method of claim 1, wherein said abrasive contact is effected by CMP.
Claim 4
Dependent Claim
27 words
The method of claim 1, wherein said at least one passivation layer is selected from the group comprising SiO 2 , Si 3 N 4 and polyimide.
Claim 5
Dependent Claim
19 words
The method of claim 1, wherein said at least one passivation layer comprises a plurality of superimposed passivation layers.
Claim 6
Dependent Claim
30 words
The method of claim 4, wherein at least one of said plurality of passivation layers is selected from the group comprising SiO 2 , Si 3 N 4 and polyimide.
Claim 7
Dependent Claim
20 words
The method of claim 1, wherein said metal layer is comprised of a plurality of sub-layers of different metallic composition.
Claim 8
Dependent Claim
43 words
The method of claim 1, wherein said integrated circuitry is in electrical communication with said at least one via through a conductive trace exposed at a bottom of said at least one via, and said metal layer is in contact with said trace.
Claim 9
Dependent Claim
17 words
The method of claim 1, wherein said forming said at least one via is effected by etching.
Claim 10
Dependent Claim
19 words
The method of claim 8, wherein said etching is selected from the group comprising sputter etching and wet etching.
Claim 11
Dependent Claim
35 words
The method of claim 9, wherein said etching comprises sputter etching effected after application of a resist layer over said at least one passivation layer defining an intended location of said at least one via.
Claim 12
Dependent Claim
35 words
The method of claim 9, wherein said etching comprises wet etching effected after application of a resist layer over said at least one passivation layer defining an intended location of said at least one via.
Claim 13
Dependent Claim
17 words
The method of claim 1, further comprising depositing a solder mass over said at least one via.
Claim 14
Dependent Claim
23 words
The method of claim 12, further comprising liquefying said solder mass and cooling said solder mass to define a solder ball or bump.
Claim 15
Independent Claim
226 words
A method of fabricating under bump metallization on a semiconductor substrate, comprising: providing a semiconductor substrate including integrated circuitry on at least one surface thereof, and at least one passivation layer having a thickness and disposed thereover; providing access to said semiconductor integrated circuitry for external contact by forming at least one via extending through said at least one passivation layer; forming a substantially conformal metal layer of a thickness substantially less than the passivation layer thickness over said at least one passivation layer with a portion of said metal layer extending into said at least one via to make electrical contact with said semiconductor integrated circuitry; applying an etchant-resistive material over said metal layer and into said at least one via so as to substantially fill said at least one via; removing said etchant-resistive material to expose said metal layer above said at least one passivation layer while having said etchant-resistive material within said at least one via; removing said metal layer over said at least one passivation layer except for the portion extending into said at least one via by applying an etchant to said exposed metal layer above said at least one passivation layer while protecting of said metal layer portion extending into said at least one via with said etchant-resistive material; and removing said etchant-resistive material within said at least one via.
Claim 16
Independent Claim
226 words
A method of fabricating under bump metallization on a semiconductor substrate, comprising: providing a semiconductor substrate including integrated circuitry on at least one surface thereof, and at least one passivation layer having a thickness and disposed thereover; providing access to said semiconductor integrated circuitry for external contact by forming at least one via extending through said at least one passivation layer; forming a substantially conformal metal layer of a thickness substantially less than the passivation layer thickness over said at least one passivation layer with a portion of said metal layer extending into said at least one via to make electrical contact with said semiconductor integrated circuitry; applying an etchant-resistive material over said metal layer and into said at least one via so as to substantially fill said at least one via; removing said etchant-resistive material to expose said metal layer above said at least one passivation layer while having said etchant-resistive material within said at least one via; removing said metal layer over said at least one passivation layer except for the portion extending into said at least one via by applying an etchant to said exposed metal layer above said at least one passivation layer while protecting of said metal layer portion extending into said at least one via with said etchant-resistive material; and removing said etchant-resistive material within said at least one via.
Claim 17
Dependent Claim
22 words
The method of claim 14, wherein said removing said etchant-resistive material over said at least one passivation layer is effected by abrasion.
Claim 18
Dependent Claim
10 words
The method of claim 15, wherein said abrasion comprises CMP.
Claim 19
Dependent Claim
56 words
The method of claim 14, wherein said removing said etchant-resistive material and removing said metal layer is effected by completely etching said etchant-resistive material and said underlying metal layer located over said at least one passivation layer, and terminating said etching prior to any substantial etching of said metal layer in said at least one via.
Claim 20
Dependent Claim
27 words
The method of claim 14, wherein said at least one passivation layer is selected from the group comprising SiO 2 , Si 3 N 4 and polyimide.
Claim 21
Dependent Claim
19 words
The method of claim 14, wherein said at least one passivation layer comprises a plurality of superimposed passivation layers.
Claim 22
Dependent Claim
30 words
The method of claim 19, wherein at least one of said plurality of passivation layers is selected from the group comprising SiO 2 , Si 3 N 4 and polyimide.
Claim 23
Dependent Claim
20 words
The method of claim 14, wherein said metal layer is comprised of a plurality of sub-layers of different metallic composition.
Claim 24
Dependent Claim
43 words
The method of claim 14, wherein said integrated circuitry is in electrical communication with said at least one via through a conductive trace exposed at a bottom of said at least one via, and said metal layer is in contact with said trace.
Claim 25
Dependent Claim
17 words
The method of claim 14, wherein said forming said at least one via is effected by etching.
Claim 26
Dependent Claim
19 words
The method of claim 23, wherein said etching is selected from the group comprising sputter etching and wet etching.
Claim 27
Dependent Claim
35 words
The method of claim 24, wherein said etching comprises sputter etching effected after application of a resist layer over, said at least one passivation layer defining an intended location of said at least one via.
Claim 28
Dependent Claim
35 words
The method of claim 24, wherein said etching comprises wet etching effected after application of a resist layer over said at least one passivation layer defining an intended location of said at least one via.
Claim 29
Dependent Claim
17 words
The method of claim 14, further comprising depositing a solder mass over said at least one via.
Claim 30
Dependent Claim
23 words
The method of claim 27, further comprising liquefying said solder mass and cooling said solder mass to define a solder ball or bump.
Claim 31
Independent Claim
170 words
A method of relocating a conductive element of a semiconductor substrate, comprising: providing a semiconductor substrate carrying integrated circuitry on at least one surface thereof, and at least one conductive element on said at least one substrate surface in communication with said circuitry, said at least one conductive element bounded by a first passivation layer over said surface; defining a conductive trace in contact with said at least one conductive element and extending over said first passivation layer to an alternative, laterally-offset conductive element location; forming a second passivation layer having a thickness over said surface and said conductive trace; etching a sloped-wall via through said second passivation layer extending to an upper surface of said conductive trace at said alternative conductive element location; forming a substantially conformal metal layer having a thickness substantially less than the second passivation layer thickness over said second passivation layer and into said sloped-wall via to make electrical contact with said conductive trace; and removing said metal layer only above said second passivation layer.
Claim 32
Independent Claim
170 words
A method of relocating a conductive element of a semiconductor substrate, comprising: providing a semiconductor substrate carrying integrated circuitry on at least one surface thereof, and at least one conductive element on said at least one substrate surface in communication with said circuitry, said at least one conductive element bounded by a first passivation layer over said surface; defining a conductive trace in contact with said at least one conductive element and extending over said first passivation layer to an alternative, laterally-offset conductive element location; forming a second passivation layer having a thickness over said surface and said conductive trace; etching a sloped-wall via through said second passivation layer extending to an upper surface of said conductive trace at said alternative conductive element location; forming a substantially conformal metal layer having a thickness substantially less than the second passivation layer thickness over said second passivation layer and into said sloped-wall via to make electrical contact with said conductive trace; and removing said metal layer only above said second passivation layer.
Claim 33
Dependent Claim
19 words
The method of claim 29, wherein said etching is selected from the group comprising sputter etching and wet etching.
Claim 34
Dependent Claim
35 words
The method of claim 30, wherein said etching comprises sputter etching effected after application of a resist layer over said second passivation layer defining an aperture aligned with said alternative bond pad conductive element location.
Claim 35
Dependent Claim
33 words
The method of claim 30, wherein said etching comprises wet etching effected after application of a resist layer over said second passivation layer defining an aperture aligned with said alternative conductive element location.
Claim 36
Dependent Claim
9 words
The method of claim 29, wherein removing comprises abrading.
Claim 37
Dependent Claim
11 words
The method of claim 33, wherein abrading is effected by CMP.
Claim 38
Dependent Claim
79 words
The method of claim 29, wherein removing said metal layer is effected by applying an etchant-resistive material over and into said sloped-wall via so as to substantially fill said sloped-wall via, removing said etchant-resistant material to expose said metal layer above said second passivation layer while leaving said etchant-resistant material with said sloped-wall via said metal layer and applying an etchant to said exposed metal layer while protecting said metal layer within said sloped-wall via with said etchant-resistant material.
Claim 39
Dependent Claim
29 words
The method of claim 35, further comprising etching said etchant-resistive material lying over said second passivation layer and a portion of said metal layer underlying said second passivation layer.
Claim 40
Dependent Claim
18 words
The method of claim 35, further comprising removing said etchant-resistive material overlying said second passivation layer by abrasion.
Claim 41
Dependent Claim
12 words
The method of claim 37, further comprising effecting said abrasion by CMP.
Claim 42
Dependent Claim
15 words
The method of claim 29, further comprising depositing a solder mass over said sloped-wall via.
Claim 43
Dependent Claim
23 words
The method of claim 39, further comprising liquefying said solder mass and cooling said solder mass to define a solder ball or bump.
Claim 44
Dependent Claim
23 words
The method of claim 29, wherein said at least one conductive element is selected from the group comprising bond pads and conductive traces.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-06 | 2001-10-06 | 2002-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-06 | 2005-10-06 | 2006-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-06 | 2009-10-06 | 2010-04-07 | $7700.00 | Window Closed / Lapsed |