US5732246A — Programmable array interconnect latch

Claim 1

Independent Claim 136 words

An integrated circuit having: a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, and at least one programmable interface circuit connected between an input interconnect lead and an output interconnect lead within said programmable interconnect network, said programmable interface circuit comprising: an input node for carrying data into said programmable interface circuit from said input interconnect lead and an output node for carrying data from said programmable interface circuit to said output interconnect lead; a circuit, connected between said input and output nodes, for selectively providing a buffered output signal to said output node, said buffered output signal being related to a logic state at said input node; and a signal storage circuit connected to said input node for selectively storing a logic state received from said input node.

Claim 2

Dependent Claim 136 words

An integrated circuit having: a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, and at least one programmable interface circuit connected between an input interconnect lead and an output interconnect lead within said programmable interconnect network, said programmable interface circuit comprising: an input node for carrying data into said programmable interface circuit from said input interconnect lead and an output node for carrying data from said programmable interface circuit to said output interconnect lead; a circuit, connected between said input and output nodes, for selectively providing a buffered output signal to said output node, said buffered output signal being related to a logic state at said input node; and a signal storage circuit connected to said input node for selectively storing a logic state received from said input node.

Claim 3

Dependent Claim 196 words

An integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, and at least one programmable interface circuit connected within said programmable interconnect network, said programmable interface circuit comprising: an input node and an output node; circuit, connected between said input and output nodes, for selectively providing a buffered output signal to said output node, said buffered output signal being related to a logic state at said input node; and a signal storage circuit connected to said input node for selectively storing a logic state received from said input node, wherein said programmable interface circuit further comprises a secondary input node and a secondary output node; and said signal storage circuit further comprises: primary selective latch selectively coupled to said input node or said secondary input node for selectively storing a logic state received from either said input node or said secondary input node; and secondary selective latch selectively coupled to said primary selective latch and coupled to said secondary output node for providing latched data to said secondary output node, said latched data being representative of a previously stored logic state of said primary selective latch.

Claim 4

Dependent Claim 196 words

An integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, and at least one programmable interface circuit connected within said programmable interconnect network, said programmable interface circuit comprising: an input node and an output node; circuit, connected between said input and output nodes, for selectively providing a buffered output signal to said output node, said buffered output signal being related to a logic state at said input node; and a signal storage circuit connected to said input node for selectively storing a logic state received from said input node, wherein said programmable interface circuit further comprises a secondary input node and a secondary output node; and said signal storage circuit further comprises: primary selective latch selectively coupled to said input node or said secondary input node for selectively storing a logic state received from either said input node or said secondary input node; and secondary selective latch selectively coupled to said primary selective latch and coupled to said secondary output node for providing latched data to said secondary output node, said latched data being representative of a previously stored logic state of said primary selective latch.

Claim 5

Dependent Claim 35 words

An integrated circuit according to claim 2 wherein said programmable interface circuit further comprises: programmable driver selectively coupled to said output node for selectively providing data representative of said latched data to said output node.

Claim 6

Dependent Claim 25 words

An integrated circuit according to claim 1 wherein each of at least some of said plurality of programmable logic cells comprises a signal storage latch.

Claim 7

Dependent Claim 18 words

An integrated circuit according to claim 1 wherein said signal storage circuit is part of a scan chain.

Claim 8

Dependent Claim 40 words

An integrated circuit according to claim 1 further comprising: first data source providing first configuration data for controlling the selectivity of said circuit; and second data source providing second configuration data for controlling the selectivity of said signal storage circuit.

Claim 9

Dependent Claim 42 words

An integrated circuit according to claim 1 wherein said programmable interface circuit further comprises: a programmable driver coupled to said output node for selectively providing data representing the stored logic state to said output node and therefore to said output interconnect lead.

Claim 10

Dependent Claim 201 words

An integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, and at least one programmable interface circuit connected within said programmable interconnect network, said programmable interface circuit comprising: an input node and an output node; a circuit, connected between said input and output nodes, for selectively providing a buffered output signal to said output node, said buffered output signal being related to a logic state at said input node; and a signal storage circuit connected to said input node for selectively storing a logic state received from said input node, wherein said integrated circuit further comprises a plurality of operational control signal paths and a plurality of test control signal paths, said integrated circuit further comprising: programmable coupler selectively connecting at least one signal path of the group consisting of at least one select operational control signal path of said plurality of operational control signal paths and at least one select test control signal path of said plurality of test control signal paths to said signal storage circuit such that said signal storage circuit can be selectively employed during testing of said integrated circuit or during operation of said integrated circuit.

Claim 11

Dependent Claim 201 words

An integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, and at least one programmable interface circuit connected within said programmable interconnect network, said programmable interface circuit comprising: an input node and an output node; a circuit, connected between said input and output nodes, for selectively providing a buffered output signal to said output node, said buffered output signal being related to a logic state at said input node; and a signal storage circuit connected to said input node for selectively storing a logic state received from said input node, wherein said integrated circuit further comprises a plurality of operational control signal paths and a plurality of test control signal paths, said integrated circuit further comprising: programmable coupler selectively connecting at least one signal path of the group consisting of at least one select operational control signal path of said plurality of operational control signal paths and at least one select test control signal path of said plurality of test control signal paths to said signal storage circuit such that said signal storage circuit can be selectively employed during testing of said integrated circuit or during operation of said integrated circuit.

Claim 12

Dependent Claim 307 words

An integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, and at least one programmable interface circuit connected within said programmable interconnect network, said programmable interface circuit comprising: an input node and an output node; a circuit, connected between said input and output nodes, for selectively providing a buffered output signal to said output node, said buffered output signal being related to a logic state at said input node; and a signal storage circuit connected to said input node for selectively storing a logic state received from said input node, wherein said signal storage circuit comprises: a secondary input node for receiving serial input data; a secondary output node for sending out serial output data; primary and secondary latches retaining respective primary and secondary latched data; a first selective coupler disposed between said input node and said primary latch, said first selective coupler selectively coupling primary data of said input node to said primary latch in accordance with a first clock signal so as to capture the primary data as said primary latched data; a second selective coupler disposed between said secondary input node and said primary latch, said second selective coupler selectively coupling serial input data of said secondary input node to said primary latch in accordance with a second clock signal so as to capture the serial input data as said primary latched data; and a third selective coupler disposed between said primary latch and said secondary latch, said third selective coupler selectively coupling said primary latch to said secondary latch in accordance with a third clock signal so as to update the secondary latched data of said secondary latch in accordance with said primary latched data, data representative of the secondary latched data being provided at said secondary output node as serial output data.

Claim 13

Dependent Claim 307 words

An integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, and at least one programmable interface circuit connected within said programmable interconnect network, said programmable interface circuit comprising: an input node and an output node; a circuit, connected between said input and output nodes, for selectively providing a buffered output signal to said output node, said buffered output signal being related to a logic state at said input node; and a signal storage circuit connected to said input node for selectively storing a logic state received from said input node, wherein said signal storage circuit comprises: a secondary input node for receiving serial input data; a secondary output node for sending out serial output data; primary and secondary latches retaining respective primary and secondary latched data; a first selective coupler disposed between said input node and said primary latch, said first selective coupler selectively coupling primary data of said input node to said primary latch in accordance with a first clock signal so as to capture the primary data as said primary latched data; a second selective coupler disposed between said secondary input node and said primary latch, said second selective coupler selectively coupling serial input data of said secondary input node to said primary latch in accordance with a second clock signal so as to capture the serial input data as said primary latched data; and a third selective coupler disposed between said primary latch and said secondary latch, said third selective coupler selectively coupling said primary latch to said secondary latch in accordance with a third clock signal so as to update the secondary latched data of said secondary latch in accordance with said primary latched data, data representative of the secondary latched data being provided at said secondary output node as serial output data.

Claim 14

Dependent Claim 51 words

An integrated circuit according to claim 9 wherein said signal storage circuit further comprises: a programmable output means for selectively outputting to said output node an output signal representative of said secondary latched data; the programmable output means selectively outputting said output signal in accordance with a first programmable select signal.

Claim 15

Dependent Claim 63 words

An integrated circuit according to claim 10 wherein said programmable output comprises a tri-state invertor having its input coupled to said secondary latch for receiving said secondary latched data, its tri-state enable coupled to be driven by said first programmable select signal, and its output coupled to said output node for providing said output signal when enabled per said first programmable select signal.

Claim 16

Dependent Claim 50 words

An integrated circuit according to claim 10 wherein said circuit connected between said input node and said output node, comprises a tri-state buffer having its input coupled to said input node, its output coupled to said output node, and its tri-state enable coupled to receive a second programmable select signal.

Claim 17

Independent Claim 174 words

A method of operating an integrated circuit, comprising the steps of: providing an integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, a programmable buffer for selectively buffering a signal within a given programmable interconnect of the programmable interconnect network, and a signal storage circuit of a first serial scan chain for selectively capturing and storing data of, and providing data to, said given programmable interconnect; configuring, as a configured logic circuit, select programmable logic cells of said plurality of logic cells and select programmable interconnects of said programmable interconnect network and including said given programmable interconnect, for implementing a desired logic design; applying data to said configured logic circuit for stimulation thereof; selectively operating said signal storage circuit for capturing data of said given programmable interconnect, as effected by processing of said configured logic circuit in response to stimulation by said data, into said signal storage circuit of said first scan chain; and scanning said captured data out of said first scan chain.

Claim 18

Independent Claim 174 words

A method of operating an integrated circuit, comprising the steps of: providing an integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, a programmable buffer for selectively buffering a signal within a given programmable interconnect of the programmable interconnect network, and a signal storage circuit of a first serial scan chain for selectively capturing and storing data of, and providing data to, said given programmable interconnect; configuring, as a configured logic circuit, select programmable logic cells of said plurality of logic cells and select programmable interconnects of said programmable interconnect network and including said given programmable interconnect, for implementing a desired logic design; applying data to said configured logic circuit for stimulation thereof; selectively operating said signal storage circuit for capturing data of said given programmable interconnect, as effected by processing of said configured logic circuit in response to stimulation by said data, into said signal storage circuit of said first scan chain; and scanning said captured data out of said first scan chain.

Claim 19

Dependent Claim 87 words

A method according to claim 13 wherein the integrated circuit also includes a second signal storage circuit of a second scan chain for receiving said data and selectively applying said data to said configured logic circuit; and said step of applying data to said configured logic circuit comprises scanning the data into said second scan chain and selectively operating said second signal storage circuit for transferring the data from said second signal storage circuit of said second scan chain to said configured logic circuit for stimulation thereof.

Claim 20

Independent Claim 149 words

A method of operating an integrated circuit, comprising the steps of: providing an integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, a programmable buffer for selectively buffering a signal within a given programmable interconnect of the programmable interconnect network, and a signal storage circuit of a serial scan chain for selectively capturing and storing data from, and providing data to, said given programmable interconnect; configuring, as a configured logic circuit, select programmable logic cells of said plurality of logic cells and select programmable interconnects of said programmable interconnect network and including said given programmable interconnect, for implementing a desired logic design; scanning data serially into said signal storage circuit via said serial scan chain; and selectively operating said signal storage circuit for presenting said data to said given programmable interconnect as input data to the configured logic circuit.

Claim 21

Independent Claim 149 words

A method of operating an integrated circuit, comprising the steps of: providing an integrated circuit having a plurality of programmable logic cells, a programmable interconnect network for connecting the programmable logic cells, a programmable buffer for selectively buffering a signal within a given programmable interconnect of the programmable interconnect network, and a signal storage circuit of a serial scan chain for selectively capturing and storing data from, and providing data to, said given programmable interconnect; configuring, as a configured logic circuit, select programmable logic cells of said plurality of logic cells and select programmable interconnects of said programmable interconnect network and including said given programmable interconnect, for implementing a desired logic design; scanning data serially into said signal storage circuit via said serial scan chain; and selectively operating said signal storage circuit for presenting said data to said given programmable interconnect as input data to the configured logic circuit.

Claim 22

Dependent Claim 43 words

A method according to claim 15, further comprising: processing said input data per the configured logic circuit; and capturing output data as effected by said processing of the configured logic circuit, into a second signal storage circuit of a second serial scan chain.

Claim 23

Independent Claim 291 words

A method of operating an integrated circuit, comprising the steps of: providing an integrated circuit having a plurality of programmable logic circuits, a programmable interconnect network for connecting the programmable logic circuits, programmable buffers for selectively buffering associated signals within respective interconnects of the programmable interconnect network, and a plurality of signal storage circuits in parallel with respective programmable buffers for selectively capturing and storing data of associated said programmable interconnects or selectively outputting stored data thereof onto associated said programmable interconnects; configuring, as a configured logic circuit, select programmable logic circuits of said plurality of logic circuits and select programmable interconnects of the programmable interconnect network, for implementing a desired logic design; configuring first select signal storage circuits of said plurality of signal storage circuits as an input serial scan chain across at least one input line of said configured logic circuit; configuring second select signal storage circuits of said plurality of signal storage circuits as an output serial scan chain across at least one output line of said configured logic circuit; scanning data into said input serial scan chain; selectively disabling the programmable buffer(s) of the select programmable interconnects as associated with said at least one input line of said configured logic circuit; selectively enabling said first select signal storage circuit of said input serial scan chain to apply the data to said configured logic circuit; processing the data by the configured logic circuit; selectively operating said second select signal storage circuits of said output serial scan chain for capturing configured logic circuit output data at said at least one output line; and selectively operating said second select signal storage circuits of said output serial scan chain for scanning said captured data out of said output serial scan chain.

Claim 24

Independent Claim 291 words

A method of operating an integrated circuit, comprising the steps of: providing an integrated circuit having a plurality of programmable logic circuits, a programmable interconnect network for connecting the programmable logic circuits, programmable buffers for selectively buffering associated signals within respective interconnects of the programmable interconnect network, and a plurality of signal storage circuits in parallel with respective programmable buffers for selectively capturing and storing data of associated said programmable interconnects or selectively outputting stored data thereof onto associated said programmable interconnects; configuring, as a configured logic circuit, select programmable logic circuits of said plurality of logic circuits and select programmable interconnects of the programmable interconnect network, for implementing a desired logic design; configuring first select signal storage circuits of said plurality of signal storage circuits as an input serial scan chain across at least one input line of said configured logic circuit; configuring second select signal storage circuits of said plurality of signal storage circuits as an output serial scan chain across at least one output line of said configured logic circuit; scanning data into said input serial scan chain; selectively disabling the programmable buffer(s) of the select programmable interconnects as associated with said at least one input line of said configured logic circuit; selectively enabling said first select signal storage circuit of said input serial scan chain to apply the data to said configured logic circuit; processing the data by the configured logic circuit; selectively operating said second select signal storage circuits of said output serial scan chain for capturing configured logic circuit output data at said at least one output line; and selectively operating said second select signal storage circuits of said output serial scan chain for scanning said captured data out of said output serial scan chain.

Claim 25

Dependent Claim 276 words

A programmable gate array, PGA, having a plurality of programmable logic circuits and a plurality of programmable interconnects, wherein at least one programmable interconnect of said plurality of programmable interconnects includes a programmable interface circuit disposed therein, said programmable interface circuit comprising: a first node coupled to a first portion of said at least one programmable interconnect; a second node coupled to a second portion said at least one programmable interconnect; a programmable coupling circuit disposed between said first and second nodes for selectively propagating a signal therebetween in accordance with a first select signal; and an LSSD register disposed between said first and second nodes, said LSSD register having: a primary input coupled to said first node for receiving primary data; a serial input for receiving serial data; first selective latch selectively coupled to said primary input or said serial input for selectively capturing, as captured data, either primary data of said primary input as effected by a pulse of a C-clock, or serial data of said serial input as effected by a pulse of an A-clock; second selective latch selectively coupled to said first selective latch for latching data therein, as latched data, corresponding to said captured data of said first selective latch, the latching of said latched data being effected by a pulse of a B-clock; a serial output for sending out serial output data corresponding to said latched data of said second selective latch; and a programmable primary output for selectively outputting to said second node primary output data corresponding to said latched data, the primary output data being selectively applied to said second node in accordance with a second select signal.

Claim 26

Dependent Claim 276 words

A programmable gate array, PGA, having a plurality of programmable logic circuits and a plurality of programmable interconnects, wherein at least one programmable interconnect of said plurality of programmable interconnects includes a programmable interface circuit disposed therein, said programmable interface circuit comprising: a first node coupled to a first portion of said at least one programmable interconnect; a second node coupled to a second portion said at least one programmable interconnect; a programmable coupling circuit disposed between said first and second nodes for selectively propagating a signal therebetween in accordance with a first select signal; and an LSSD register disposed between said first and second nodes, said LSSD register having: a primary input coupled to said first node for receiving primary data; a serial input for receiving serial data; first selective latch selectively coupled to said primary input or said serial input for selectively capturing, as captured data, either primary data of said primary input as effected by a pulse of a C-clock, or serial data of said serial input as effected by a pulse of an A-clock; second selective latch selectively coupled to said first selective latch for latching data therein, as latched data, corresponding to said captured data of said first selective latch, the latching of said latched data being effected by a pulse of a B-clock; a serial output for sending out serial output data corresponding to said latched data of said second selective latch; and a programmable primary output for selectively outputting to said second node primary output data corresponding to said latched data, the primary output data being selectively applied to said second node in accordance with a second select signal.

Claim 27

Dependent Claim 41 words

A PGA according to claim 18 wherein said programmable coupling circuit includes a tri-state buffer with its input coupled to said first node, its output coupled to said second node and its tri-state enable coupled to receive said first select signal.

Claim 28

Dependent Claim 43 words

A PGA according to claim 19 wherein said programmable coupling circuit further comprises a second tri-state buffer with its input coupled to said second node, its output coupled to said first node and its tri-state enable coupled to receive a third select signal.

Claim 29

Dependent Claim 14 words

A PGA according to claim 19 wherein said tri-state buffer comprises a tri-state inverter.

Claim 30

Dependent Claim 44 words

A PGA according to claim 19 wherein said programmable coupling circuit further comprises a pass gate disposed between said first node and said second node, said pass gate selectively coupling said first node to said second node in accordance with a third select signal.

Claim 31

Dependent Claim 92 words

A PGA according to claim 18 further comprising: a plurality of memory cells associated with respective programmable resources of said PGA; a first memory cell of said plurality of memory cells being associated with said programmable coupling circuit and providing said first select signal in accordance with data stored in said first memory cell; and a second memory cell of said plurality of memory cells being associated With said programmable primary output of said LSSD register and providing said second select signal in accordance with data stored in said second memory cell.

Claim 32

Dependent Claim 68 words

A programmed PGA according to claim 23 wherein said first memory cell has been loaded with data so as to configure said programmable coupling circuit to propagate a signal between said first and second nodes; and said second memory cell has been loaded with data so as to configure said programmable primary output of said LSSD register to apply the primary output data thereof to said second node.

Claim 33

Dependent Claim 57 words

A computing system employing a PGA according to claim 23, further comprising: configuration means for providing predetermined first and second configuration data for storage as said associated stored data in said first and second memory cells respectively in accordance with desired configuration states of said programmable coupling circuit and said programmable primary output of said LSSD register.

Claim 34

Dependent Claim 57 words

A computing system according to claim 25 wherein said configuration means comprises a memory device of the group consisting of RAM, ROM, EPROM and EEPROM, said memory device having a data structure memory map allocated to the programmable resources of said PGA inclusive of said programmable coupling circuit and said programmable primary output of said LSSD register.

Claim 35

Dependent Claim 46 words

A PGA according to claim 18 wherein said programmable primary output of said LSSD register comprises a tri-state buffer having its output coupled to said second node, its input coupled to receive said latched data, and its tri-state enable coupled to receive said second select signal.

Claim 36

Dependent Claim 70 words

A PGA according to claim 18 wherein said LSSD register is one of a plurality of LSSD registers providing a serial scan chain, adjacent LSSD registers of said plurality of LSSD registers having respective serial inputs/outputs coupled to neighboring serial outputs/inputs, the plurality of LSSD registers of said serial scan chain sharing in common respective A, B, C-clocks, and receiving independent said second select signals for respective programmable primary outputs.

Claim 37

Dependent Claim 151 words

A PGA according to claim 18 further comprising: a plurality of functional clock lines for propagating various system clock signals for clocking associated configured logic circuits of said plurality of programmable logic circuits during functional operation of said associated configured logic circuits; a plurality of test clock lines for propagating test clock signals for clocking said LSSD register during testing of said PGA; and programmable selection means for alternatively coupling either at least one select functional clock line of said plurality of functional clock lines or at least one select test clock line of the plurality of test clock lines to said LSSD register as associated said A, B, C-clocks thereof, so that said LSSD register may be clocked by the associated at least one functional clock signal during functional operation of said PGA or alternatively clocked by the associated at least one test clock signal during testing of said PGA.

Claim 38

Dependent Claim 22 words

A PGA according to claim 29 wherein the programmable selection means selectively provides the C and B clocks of said LSSD register.

Claim 39

Dependent Claim 14 words

A PGA according to claim 29 wherein the programmable selection means comprises a multiplexer.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-03-23	2001-09-22	2002-03-24	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-03-23	2005-09-22	2006-03-24	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-03-23	2009-09-22	2010-03-24	$7700.00	Window Closed / Lapsed

Programmable array interconnect latch

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