Circuitry and method for latching a logic state

Claim 2

Circuitry for latching a logic state, comprising: an input node for inputting an input signal; first transfer circuitry coupled to said input node for outputting a first signal indicating a logic state of said input signal in response to a first transition of a clock signal; second transfer circuitry coupled to said first transfer circuitry for outputting a second signal indicating a logic state of said first signal in response to a second transition of said clock signal; and multiplexing circuitry coupled to said first and second transfer circuitry for outputting an output signal indicating said logic state of said first signal in response to said second transition and indicating a logic state of said second signal in response to said first transition.

Claim 3

The circuitry of claim 1 and including latching circuitry coupled to said first transfer circuitry for latching said first signal.

Claim 4

The circuitry of claim 2 wherein said latching circuitry latches said first signal in response to said second transition.

Claim 5

The circuitry of claim 1 and including latching circuitry coupled said second transfer circuitry for latching said second signal.

Claim 6

The circuitry of claim 4 wherein said latching circuitry latches said second signal in response to said first transition.

Claim 7

The circuitry of claim 1 wherein said second transfer circuitry outputs said second signal indicating said logic state of said first signal by outputting said second signal having a logic state inverted from that of said first signal.

Claim 8

The circuitry of claim 1 wherein said first transfer circuitry outputs said first signal indicating said logic state of said input signal by outputting said first signal having a logic state equal to that of said input signal.

Claim 9

The circuitry of claim 1 wherein said first transfer circuitry is coupled through an inverter to said input node, and wherein said first transfer circuitry outputs said first signal indicating said logic state of said input signal by outputting said first signal having a logic state inverted from that of said input signal.

Claim 10

The circuitry of claim 1 wherein said multiplexing circuitry includes: a driver section for controlling said output signal to indicate said logic state of said first signal in response to said second transition; and a holder section for controlling said output signal to indicate said logic state of said second signal in response to said first transition.

Claim 11

The circuitry of claim 9 wherein said driver section controls said output signal to indicate said logic state of said first signal by controlling said output signal to have a logic state inverted from that of said first signal.

Claim 12

The circuitry of claim 9 wherein said holder section controls said output signal to indicate said logic state of said second signal by controlling said output signal to have a logic state inverted from that of said second signal.

Claim 13

The circuitry of claim 1 wherein said first transition of said clock signal is opposite in direction from said second transition of said clock signal.

Claim 14

Circuitry for latching a logic state, comprising: an input node for inputting an input signal; clock circuitry for outputting a clock signal; a first transfer gate coupled to said input node and to said clock circuitry for outputting a first signal indicating a logic state of said input signal in response to a first transition of said clock signal; a first latch coupled to said first transfer gate for latching said first signal; a second transfer gate coupled to said first latch and to said clock circuitry for outputting a second signal indicating a logic state of said first signal in response to a second transition of said clock signal; a second latch coupled to said second transfer gate for latching said second signal; and a multiplexer coupled to said first and second latches and to said clock circuitry for outputting an output signal indicating said logic state of said first signal in response to said second transition and indicating a logic state of said second signal in response to said first transition.

Claim 15

Circuitry for latching a logic state, comprising: an input node for inputting an input signal; clock circuitry for outputting a clock signal; a first transfer gate coupled to said input node and to said clock circuitry for outputting a first signal indicating a logic state of said input signal in response to a first transition of said clock signal; a first latch coupled to said first transfer gate for latching said first signal; a second transfer gate coupled to said first latch and to said clock circuitry for outputting a second signal indicating a logic state of said first signal in response to a second transition of said clock signal; a second latch coupled to said second transfer gate for latching said second signal; and a multiplexer coupled to said first and second latches and to said clock circuitry for outputting an output signal indicating said logic state of said first signal in response to said second transition and indicating a logic state of said second signal in response to said first transition.

Claim 16

The circuitry of claim 13 wherein said first latch includes first and second inverters, an input of said first inverter being coupled to said transfer gate, an output of said first inverter being coupled to an input of said second inverter, and an output of said second inverter being coupled to said input of said first inverter.

Claim 17

The circuitry of claim 14 wherein said multiplexer is coupled to said first latch by being coupled to said input of said first inverter.

Claim 18

The circuitry of claim 14 wherein said multiplexer is coupled to said first latch by being coupled to said output of said first inverter.

Claim 19

The circuitry of claim 14 wherein said second inverter includes a gated inverter coupled to said clock circuitry, such that said first latch latches said first signal in response to said second transition.

Claim 20

The circuitry of claim 13 wherein said second latch is coupled to said clock circuitry and latches said second signal in response to said first transition.

Claim 21

The circuitry of claim 13 wherein said multiplexer includes: a driver section for controlling said output signal to indicate said logic state of said first signal in response to said second transition; and a holder section for controlling said output signal to indicate said logic state of said second signal in response to said first transition.

Claim 22

The circuitry of claim 19 wherein said clock circuitry is operable to output an inverted clock signal inverted from said clock signal, and wherein said driver section includes: a first p-channel field effect transistor having a gate coupled to said first latch, a source coupled to a voltage supply node, and a drain; a second p-channel field effect transistor having a gate coupled to said clock circuitry for receiving said inverted clock signal, a source coupled to said drain of said first p-channel field effect transistor, and a drain coupled to a first output node; a first n-channel field effect transistor having a gate coupled to said gate of said first p-channel field effect transistor, a source coupled to a voltage reference node, and a drain; and a second n-channel field effect transistor having a gate coupled to said clock circuitry for receiving said clock signal, a source coupled to said drain of said first n-channel field effect transistor, and a drain coupled to said first output node.

Claim 23

The circuitry of claim 20 wherein said holder section includes: a third p-channel field effect transistor having a gate coupled to said second latch, a source coupled to said voltage supply node, and a drain; a fourth p-channel field effect transistor having a gate coupled to said clock circuitry for receiving said clock signal, a source coupled to said drain of said third p-channel field effect transistor, and a drain coupled to a second output node; a third n-channel field effect transistor having a gate coupled to said gate of said third p-channel field effect transistor, a source coupled to said voltage reference node, and a drain; and a fourth n-channel field effect transistor having a gate coupled to said clock circuitry for receiving said inverted clock signal, a source coupled to said drain of said third n-channel field effect transistor, and a drain coupled to said second output node.

Claim 24

The circuitry of claim 21 wherein said first output node is coupled to said second output node for outputting said output signal.

Claim 25

The circuitry of claim 13 wherein said first transition is a positive edge transition of said clock signal, and said second transition is a negative edge transition of said clock signal.

Claim 26

The circuitry of claim 13 wherein said first transition is a negative edge transition of said clock signal, and said second transition is a positive edge transition of said clock signal.

Claim 29

The method of claim 25 and including the step of latching said first signal.

Claim 30

The method of claim 26 wherein said step of latching said first signal includes the step of latching said first signal in response to said second transition.

Claim 31

The method of claim 27 and including the step of latching said second signal.

Claim 32

The method of claim 28 wherein said step of latching said second signal includes the step of latching said second signal in response to said first transition.

Claim 33

The method of claim 25 wherein said step of outputting said second signal indicating said logic state of said first signal includes the step of outputting said second signal having a logic state inverted from that of said first signal.

Claim 34

The method of claim 25 wherein said step of outputting said first signal indicating said logic state of said input signal includes the step of outputting said first signal having a logic state equal to that of said input signal.

Claim 35

Circuitry for latching a logic state, comprising: an input node for inputting an input signal; transfer circuitry coupled to the input node for outputting a first signal indicating a logic state of said input signal in response to a first transition of a reference signal and for outputting a second signal indicating a logic state of the first signal in response to a second transition of the reference signal; and circuitry coupled to the transfer circuitry for outputting an output signal indicating the logic state of the first signal in response to the second transition and indicating a logic state of the second signal in response to the first transition.

Claim 36

Circuitry for latching a logic state, comprising: an input node for inputting an input signal; transfer circuitry coupled to the input node for outputting a first signal indicating a logic state of said input signal in response to a first transition of a reference signal and for outputting a second signal indicating a logic state of the first signal in response to a second transition of the reference signal; and circuitry coupled to the transfer circuitry for outputting an output signal indicating the logic state of the first signal in response to the second transition and indicating a logic state of the second signal in response to the first transition.

Claim 37

The circuitry for latching a logic state of claim 32, wherein said reference signal is a clock signal.