Patent FR2373777A2 successfully refreshed from Google Patents.
US4476431A
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Shift register latch circuit means contained in LSI circuitry conforming to level sensitive scan design (LSSD) rules and techniques and utilized at least in part for check and test purposes
Assignee: International Business Machines Corp
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Filing: 1981-05-18
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Granted: 1984-10-09
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Expires: 2001-05-18
Abstract
Abstract LSI circuitry conforming to LSSD rules and techniques usually requires at least a small portion of circuitry used only for check and test purposes. The disclosed circuitry meets the LSSD design rules and techniques and considerably reduces the test circuit overhead. The disclosure modifies the known shift register latch (SRL) strategy by logically removing the master latches from the slave latches and by providing the slave latches with multiple shift inputs, e.g., two shift inputs (FIG. 2). The LSSD shifting philosophy remains unchanged to the extent that at the time of shifting, the virtual (not available slave latch) becomes real (physical) by assigning the only physical slave latch to the respective master latch. The present disclosure provides for multiple master latches to be dynamically assigned to one slave latch during shifting. This is in contrast to the known SRL chain approach requiring one slave latch for each master latch. Level Sensitive Scan Design Rules and Techniques are extensively disclosed in the testing art. See for example (1) U.S. Pat. No. 3,783,254 entitled "Level Sensitive Logic System" filed Oct. 16, 1972, granted Jan. 1, 1974 to E. B. Eichelberger, of common assignee herewith, or; (2) "A Logic Design Structure for LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, pages 462-468, June 20, 21 and 22, 1977, New Orleans, Louisiana, IEEE Catalog Number 77, CH1216-1C.
Inventors
- 👤 Arnold Blum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:44
CPC Classifications
G; G11; G11C; G11C19/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31707; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
192 words
In a functional logic unit for performing at least one logical function, said functional logic unit including shift register latch circuit means, said shift register latch circuit means comprising: m master latch circuits, each master latch circuit having an input and an output, where m is a positive integer; said m master latch circuits being interconnected into k groups of master latch circuits; n slave latch circuits, each slave latch circuit having an input and an output, where n is a positive integer and m=kn; and controllable circuit means interconnecting each of said k groups of master latch circuits with said n slave latch circuits for forming any one of k shift registers at a given instant in time, and wherein each one of said k shift registers includes a distinct one of said k groups of master latch circuits interconnected with said n slave latch circuits, each one of said k shift registers having n shift register stages, an input, and an output and where each of said n shift register stages is a shift register latch consisting of a master latch circuit and one of said n slave latch circuits.
Claim 2
Dependent Claim
192 words
In a functional logic unit for performing at least one logical function, said functional logic unit including shift register latch circuit means, said shift register latch circuit means comprising: m master latch circuits, each master latch circuit having an input and an output, where m is a positive integer; said m master latch circuits being interconnected into k groups of master latch circuits; n slave latch circuits, each slave latch circuit having an input and an output, where n is a positive integer and m=kn; and controllable circuit means interconnecting each of said k groups of master latch circuits with said n slave latch circuits for forming any one of k shift registers at a given instant in time, and wherein each one of said k shift registers includes a distinct one of said k groups of master latch circuits interconnected with said n slave latch circuits, each one of said k shift registers having n shift register stages, an input, and an output and where each of said n shift register stages is a shift register latch consisting of a master latch circuit and one of said n slave latch circuits.
Claim 3
Dependent Claim
587 words
In an integrated circuit device, test circuit means for at least assisting in the testing of said integrated circuit device, said test circuit means comprising shift register latch circuit means including: a first group of one through n master latch circuits, each of said master latch circuits having a data input, a clock input, and an output, where n is a positive integer; a second group of one through n master latch circuits, each of said master latch circuits having a data input, a clock input and an output; a group of one through n slave latch circuits, each of said slave latch circuits having a data input, clock input, and an output; a first group of one through n AND circuits, each of said AND circuits of said first group having first and second inputs and an output; a second group of one through n AND circuits, each of said AND circuits of said second group having first and second inputs and an output; a shift register latch circuit means input, said shift register latch circuit means input being connected to said data input of said first master latch circuit of each of said first and second groups of master latch circuits; a shift register latch circuit means output, said shift register latch circuit means output being connected to said output of said nth slave latch circuit of said one through n slave latch circuits; first connection means, said first connection means respectively connecting the outputs of said first through the n-1th slave latch circuits, singly in the order designated, to each of said data inputs of said second through nth master latch circuits of said first group of master latch circuits, and singly in the order designated, to each of said data inputs of said second through nth master latch circuits of said second group of master latch circuits; second connection means, said second connection means respectively connecting the outputs of said first through nth master latch circuits of said first group of master latch circuits, singly in the order designated, to the first input of said one through n AND circuits of said first group of AND circuits; third connection means, said third connection means respectively connecting the outputs of said first through nth master latch circuits of said second group of master latch circuits, singly in the order designated, to the first input of said one through n AND circuits of said second group of AND circuits; fourth connection means, said fourth connection means respectively connecting the first through nth outputs of said first group of AND circuits, singly in the order designated, to the data inputs of said first through nth slave latch circuits; fifth connection means, said fifth connection means respectively connecting the first through nth outputs of said second group of AND circuits, singly in the order designated, to the data inputs of said first through nth slave latch circuits; a first source of clock A pulses; a second source of clock B pulses; a control signal source for providing a control signal; controllable circuit means connected to said first and second clock pulse sources and said control signal source, said controllable circuit means being connected to said clock inputs of said first through nth master latch circuits of said first and second groups of master circuit latch circuits, said clock inputs of said first through nth slave latch circuits and said second inputs of said first through nth AND circuits of said first and second groups of AND circuits.
Claim 4
Dependent Claim
587 words
In an integrated circuit device, test circuit means for at least assisting in the testing of said integrated circuit device, said test circuit means comprising shift register latch circuit means including: a first group of one through n master latch circuits, each of said master latch circuits having a data input, a clock input, and an output, where n is a positive integer; a second group of one through n master latch circuits, each of said master latch circuits having a data input, a clock input and an output; a group of one through n slave latch circuits, each of said slave latch circuits having a data input, clock input, and an output; a first group of one through n AND circuits, each of said AND circuits of said first group having first and second inputs and an output; a second group of one through n AND circuits, each of said AND circuits of said second group having first and second inputs and an output; a shift register latch circuit means input, said shift register latch circuit means input being connected to said data input of said first master latch circuit of each of said first and second groups of master latch circuits; a shift register latch circuit means output, said shift register latch circuit means output being connected to said output of said nth slave latch circuit of said one through n slave latch circuits; first connection means, said first connection means respectively connecting the outputs of said first through the n-1th slave latch circuits, singly in the order designated, to each of said data inputs of said second through nth master latch circuits of said first group of master latch circuits, and singly in the order designated, to each of said data inputs of said second through nth master latch circuits of said second group of master latch circuits; second connection means, said second connection means respectively connecting the outputs of said first through nth master latch circuits of said first group of master latch circuits, singly in the order designated, to the first input of said one through n AND circuits of said first group of AND circuits; third connection means, said third connection means respectively connecting the outputs of said first through nth master latch circuits of said second group of master latch circuits, singly in the order designated, to the first input of said one through n AND circuits of said second group of AND circuits; fourth connection means, said fourth connection means respectively connecting the first through nth outputs of said first group of AND circuits, singly in the order designated, to the data inputs of said first through nth slave latch circuits; fifth connection means, said fifth connection means respectively connecting the first through nth outputs of said second group of AND circuits, singly in the order designated, to the data inputs of said first through nth slave latch circuits; a first source of clock A pulses; a second source of clock B pulses; a control signal source for providing a control signal; controllable circuit means connected to said first and second clock pulse sources and said control signal source, said controllable circuit means being connected to said clock inputs of said first through nth master latch circuits of said first and second groups of master circuit latch circuits, said clock inputs of said first through nth slave latch circuits and said second inputs of said first through nth AND circuits of said first and second groups of AND circuits.
Claim 5
Dependent Claim
150 words
In an integrated circuit device, test circuitry means for at least assisting in the testing of said integrated circuit device, said test circuit means comprising shift register latch circuit means, as recited in claim 2, wherein said controllable circuit means consists essentially of logical circuit means, said logical circuit means in response to said control signal providing a first output manifestation, or a second output manifestation, whereby in response to said first output manifestation said first group of master latch circuits and said group of slave latch circuits are interconnected to function as a first shift register having an input, an output and n shift register latch stages, and in response to said second output manifestation, said second group of master latch circuits and said group of slave latch circuits are interconnected to function as a second shift register having an input an output and n shift register latch stages.
Claim 6
Dependent Claim
102 words
In an integrated circuit device, test circuitry means for at least assisting in the testing of said integrated circuit device, said test circuit means comprising shift register latch circuit means, as recited in claim 3, wherein in response to said first output manifestation of said controllable circuit means, said clock pulses from said first source of clock A pulses are impressed on said clock inputs of said first group of master latch circuits and said B clock pulses of said second source of clock pulses are impressed on said second inputs of said AND circuits of said first group of AND circuits.
Claim 7
Dependent Claim
102 words
In an integrated circuit device, test circuitry means for at least assisting in the testing of said integrated circuit device, said test circuit means comprising shift register latch circuit means, as recited in claim 3, wherein in response to said second output manifestation of said controllable circuit means, said clock pulses from said first source of clock A pulses are impressed on said clock inputs of said second group of master latch circuits and said clock pulses of said second source of clock B pulses are impressed on said second inputs of said AND circuits of said second group of AND circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-09 | 1988-04-09 | 1988-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-09 | 1992-04-09 | 1992-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-09 | 1996-04-09 | 1996-10-09 | $7700.00 | Window Closed / Lapsed |