Clock generation network for level sensitive logic system

Claim 2

A semiconductor chip containing integrated circuitry for use in a digital computer of the like, comprising: a plurality of networks at least one of which is a combinational logic network, at least one of said networks being responsive to a set of input signals with each network providing at least a first set of signals; a clock generation system for generating a plurality of clock signal trains wherein the signals of each of said plurality of clock signal trains is non-overlapping in time duration with the signals of each other ones of said plurality of clock signal trains; plural sequential circuit means arranged in groups coupled to respective ones of said plurality of networks for receiving respective first sets of signals from said network under control of predetermined ones of said non-overlapping clock signal trains to store indications of the signals from its associated network and to provide a set of outputs for said indications; means coupling said output indications from the respective groups of plural sequential circuit means as sets of inputs to all networks except a network coupled to a sequential circuit means controlled by the clock signal train exercising control in providing the set of output indications. means for accepting the sets of output indications to provide an output response from said chip; said integrated circuitry on said semiconductor chip being further characterized in that said clock generation system wholly contained on and within said semiconductor chip comprises: a chip input terminal for receiving a periodic input; a plurality of interconnected logical circuit means connected to said input terminal; each of said plurality of logical circuit means providing a discrete one of said plurality of non-overlapping clock signal trains.

Claim 3

In a semiconductor chip as recited in claim 1 wherein said clock generation system is further characterized by the inclusion of test circuit means having at least one chip input terminal for use in testing said plurality of interconnected logical circuit means and the time occurrence of said clock signals of each of said non-overlapping clock signal trains.

Claim 4

In a semiconductor chip as recited in claim 2 wherein the combination of said plurality of interconnected logical circuit means and said test circuit means comprises Inverter circuit means and AND circuit means.

Claim 5

A semiconductor chip as recited in claim 3, wherein the number of groups of sequential circuit means is equivalent to the number of clock signal trains and each group is controlled by a different one of said trains.

Claim 6

A semiconductor chip as recited in claim 4 wherein said trains are non-overlapping and a predetermined duration exists between the occurrence of signals in successive trains, said duration being greater than the longest propagation time through said networks.

Claim 7

A semiconductor chip as recited in claim 5 wherein the combination logic network further provides a second set of combinational signals and means are provided with each group of sequential circuit means coupled to said combinational network to render the groups responsive only to the presence of respective second sets of signals and the clock signal train for that group, whereby the first sets of signals from the networks are stored in respective groups.

Claim 8

A semiconductor chip as recited in claim 6, wherein each of the plural sequential circuit means includes means for providing access to them independent of the clock signal train control and the access means of each of said sequential circuit means are coupled together for providing scan in/scan out of said integrated circuitry of said semiconductor chip.

Claim 9

A semiconductor chip, as recited in claim 7 wherein each of the sequential circuit means comprises first and second bistable storage circuits with the first of said circuits coupled to a respective one of said networks and to a clock signal train and operative to provide one of said set of outputs and said second bistable circuit is coupled to the output of the associated first bistable network, and said access means comprises input means coupled to said first circuit, output means coupled to said second circuit and means for controlling the entry of data into the first circuit and exit of said data from the second circuit independent of the clock signal train control.

Claim 10

A semiconductor chip, as recited in claim 8, wherein the entry and exit control means are coupled to all of said sequential circuit means and said sequential circuit means coupled together in cascade with output of each said second bistable circuit except the last coupled as an input to the next succeeding first bistable circuit, the first bistable circuit receiving an independent data input and the last second bistable circuit providing an independent data output, whereby said plural sequential circuit means are coupled together as a register for accomplishing said scan in/scan out of said integrated circuitry of said semiconductor chip.

Claim 11

A functional logic unit for performing at least one predetermined logical function wherein the circuitry is organized and arranged to facilitate testing said unit, said unit comprising: a plurality of networks at least one of which is a combinational logic network, at least one of said networks being responsive to a set of input signals with each network providing at least a first set of signals; a clock generation system for generating a plurality of clock signal trains wherein the signals of each of said plurality of clock signal trains is non-overlapping in time duration with the signals of each other ones of said plurality of clock signal trains; plural sequential circuit means arranged in groups coupled to respective ones of said plurality of networks for receiving respective first sets of signals from said network under control of predetermined ones of said non-overlapping clock signal trains to store indications of the signals from its associated network and to provide a set of outputs for said indications; means coupling said output indications from the respective groups of plural sequential circuit means as sets of inputs to all networks except a network coupled to a sequential circuit means controlled by the clock signal train exercising control in providing the set of output indications; means for accepting the sets of output indications to provide an output response from said unit; said functional unit being further characterized in that said clock generation system includes: at least one unit input terminal for receiving a periodic input; at least first and second interconnected logical circuit means connected to said input terminal; each of said logical circuit means providing a discrete one of said plurality of non-overlapping clock signal trains, each of said plurality of logical circuit means being level sensitive and single sided delay dependent.

Claim 12

A functional logic unit for performing at least one predetermined logical function wherein the circuitry is organized and arranged to facilitate testing said unit, said unit comprising: a plurality of networks at least one of which is a combinational logic network, at least one of said networks being responsive to a set of input signals with each network providing at least a first set of signals; a clock generation system for generating a plurality of clock signal trains wherein the signals of each of said plurality of clock signal trains is non-overlapping in time duration with the signals of each other ones of said plurality of clock signal trains; plural sequential circuit means arranged in groups coupled to respective ones of said plurality of networks for receiving respective first sets of signals from said network under control of predetermined ones of said non-overlapping clock signal trains to store indications of the signals from its associated network and to provide a set of outputs for said indications; means coupling said output indications from the respective groups of plural sequential circuit means as sets of inputs to all networks except a network coupled to a sequential circuit means controlled by the clock signal train exercising control in providing the set of output indications; means for accepting the sets of output indications to provide an output response from said unit; said functional unit being further characterized in that said clock generation system includes: at least one unit input terminal for receiving a periodic input; at least first and second interconnected logical circuit means connected to said input terminal; each of said logical circuit means providing a discrete one of said plurality of non-overlapping clock signal trains, each of said plurality of logical circuit means being level sensitive and single sided delay dependent.

Claim 13

A functional unit as recited in claim 10 wherein said clock generation system is further characterized by the inclusion of test circuit means having at least one input terminal for use in testing said interconnected logical circuit means and the time occurrence of said clock signals of each of said non-overlapping clock signal trains and wherein in combination said interconnected logical circuit means and said test circuit means comprises Inverter Circuit means and AND circuit means.

Claim 14

A functional unit as recited in claim 10 where said first interconnected logical circuit means includes a first AND circuit having at least first and second inputs and an output, a first integer number of inverter circuits serially connected between said unit input terminal and said first input of said first AND circuit, an additional inverter circuit, having an input and an output and connecting said second input of said first AND circuit to said unit input terminal, and said second interconnected logical circuit means includes a second AND circuit having at least first and second inputs and an output, connection means directly connecting said first input of said second AND circuit to said unit input terminal, and a second integer number of inverter circuits serially connected between said second input terminal of said second AND circuit and said output of said additional inverter circuit.

Claim 15

A functional unit as recited in claim 12, wherein said additional inverter circuit, each of said first integer number of inverter circuits and each of said second integer number of inverter circuits have equal time delay characteristics.

Claim 16

A functional unit as recited in claim 13 wherein said first integer number is equal to or greater than said second integer number.

Claim 17

A functional unit, as recited in claim 14, wherein said first AND circuit and said second AND circuit each have a third input utilized for test purposes.

Claim 18

A clock generation network for providing first and second pulse trains, where each said pulse in said first pulse train is precisely time displaced from each said corresponding pulse in said second pulse train, said clock generation network comprising: an input terminal for receiving a periodic input; first and second interconnected logical circuit means connected to said input terminal; said first logical circuit means comprised of inverter circuit means and AND circuit means having an output for electrically manifesting said first pulse train; said second logical circuit means comprised of inverter circuit means and AND circuit means having an output for electrically manifesting said second pulse train.

Claim 19

A clock generation network for providing first and second pulse trains, where each said pulse in said first pulse train is precisely time displaced from each said corresponding pulse in said second pulse train, said clock generation network comprising: an input terminal for receiving a periodic input; first and second interconnected logical circuit means connected to said input terminal; said first logical circuit means comprised of inverter circuit means and AND circuit means having an output for electrically manifesting said first pulse train; said second logical circuit means comprised of inverter circuit means and AND circuit means having an output for electrically manifesting said second pulse train.

Claim 20

A clock generation network as recited in claim 16 wherein said AND circuit means of said first logical circuit means and said AND circuit means of said second logical circuit means respectively include an additional dummy input for use in testing said clock generation network.

Claim 21

A clock generation network as recited in claim 16 wherein, said AND circuit means of said first and second logic circuit means respectively include a first input connected to said inverter circuit means of said first logical circuit means, a second input connected to said inverter circuit means of said second logical circuit means, and a third input respectively connected to a discrete test input terminal.

Claim 22

A level sensitive logic system for use in a digital computer of the like, comprising: a plurality of networks at least one of which is a combinational logic network, at least one of said networks being responsive to a set of input signals with each network providing at least a first set of signals; a clock generation system for generating a plurality of clock signal trains wherein the signals of each of said plurality of clock signal trains is non-overlapping in time duration with the signals of each other ones of said plurality of clock signal trains; plural sequential circuit means arranged in groups coupled to respective ones of said plurality of networks for receiving respective first sets of signals from said network under control of predetermined ones of said non-overlapping clock signal trains to store indications of the signals from its associated network and to provide a set of outputs for said indications; means coupling said output indications from the respective groups of plural sequential circuit means as sets of inputs to at least certain networks except a network coupled to a sequential circuit means controlled by the clock signal train exercising control in providing the set of output indications; means for accepting the sets of output indications to provide an output response from said system; said level sensitive logic system being further characterized by said clock generation system comprising: a chip input terminal for receiving a periodic input; a plurality of interconnected logical circuit means connected to said input terminal; each of said plurality of logical circuit means providing a discrete one of said plurality of non-overlapping clock signal trains.

Claim 23

A level sensitive logic system for use in a digital computer of the like, comprising: a plurality of networks at least one of which is a combinational logic network, at least one of said networks being responsive to a set of input signals with each network providing at least a first set of signals; a clock generation system for generating a plurality of clock signal trains wherein the signals of each of said plurality of clock signal trains is non-overlapping in time duration with the signals of each other ones of said plurality of clock signal trains; plural sequential circuit means arranged in groups coupled to respective ones of said plurality of networks for receiving respective first sets of signals from said network under control of predetermined ones of said non-overlapping clock signal trains to store indications of the signals from its associated network and to provide a set of outputs for said indications; means coupling said output indications from the respective groups of plural sequential circuit means as sets of inputs to at least certain networks except a network coupled to a sequential circuit means controlled by the clock signal train exercising control in providing the set of output indications; means for accepting the sets of output indications to provide an output response from said system; said level sensitive logic system being further characterized by said clock generation system comprising: a chip input terminal for receiving a periodic input; a plurality of interconnected logical circuit means connected to said input terminal; each of said plurality of logical circuit means providing a discrete one of said plurality of non-overlapping clock signal trains.

Claim 24

A level sensitive logic system as recited in claim 19 where in each of said plurality of interconnected logical circuit means includes a discrete test terminal.

Claim 25

A level sensitive logic system as recited in claim 20 wherein said system is contained on at least first and second interconnected integrated circuit semiconductor chips.