Patent US3637684A successfully refreshed from Google Patents.
Patent US5729762A successfully refreshed from Google Patents.
US5729762A
Expired / Lapsed
US
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Input output controller having interface logic coupled to DMA controller and plurality of address lines for carrying control information to DMA agent
Assignee: Intel Corp
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Filing: 1995-04-21
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Granted: 1998-03-17
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Expires: 2015-04-21
Abstract
Abstract A computer system performs direct memory access (DMA) transfers according to a DMA transfer protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. A DMA agent, system memory, and a DMA controller are coupled to the bus. The DMA controller uses the electrical interface of the PCI bus to control a DMA transfer between system memory and the DMA agent. According to one embodiment, a system I/O controller is coupled between the DMA controller and the PCI bus. The system I/O controller passes DMA control information from the DMA controller to the DMA agent using the electrical interface of the PCI bus. The electrical interface of the PCI bus includes a plurality of address lines and a grant signal line coupled to the DMA agent, wherein the system that I/O controller transmits DMA control information to the DMA agent while asserting the grant signal line.
Inventors
- 👤 James P. Kardach
- 👤 Sung-Soo Cho
- 👤 Debra T. Cohen
- 👤 John W. Horigan
- 👤 Neil W. Songer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:30
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
134 words
A computer system comprising: a processor; a local bus coupled to the processor; a direct memory access (DMA) agent configured to request direct access to a memory device; and a system input/output (I/O) controller coupled to the local bus, including: a direct memory access (DMA) controller; interface logic coupled to the DMA controller and configured to communicate over the local bus according to a local bus protocol; a plurality of control/byte enable lines coupled to the interface logic wherein the control/byte enable lines carry control and byte enable information in a time multiplexed manner; and a plurality of address lines coupled to the interface logic, including address lines that carry DMA control information from the DMA controller to the DMA agent through the interface logic, the control information including a type of DMA cycle.
Claim 2
Dependent Claim
134 words
A computer system comprising: a processor; a local bus coupled to the processor; a direct memory access (DMA) agent configured to request direct access to a memory device; and a system input/output (I/O) controller coupled to the local bus, including: a direct memory access (DMA) controller; interface logic coupled to the DMA controller and configured to communicate over the local bus according to a local bus protocol; a plurality of control/byte enable lines coupled to the interface logic wherein the control/byte enable lines carry control and byte enable information in a time multiplexed manner; and a plurality of address lines coupled to the interface logic, including address lines that carry DMA control information from the DMA controller to the DMA agent through the interface logic, the control information including a type of DMA cycle.
Claim 3
Dependent Claim
29 words
The computer system of claim 1, wherein the type of DMA cycle includes: a normal read cycle; a normal write cycle; a verify cycle; and a terminal count cycle.
Claim 4
Dependent Claim
36 words
The computer system of claim 1, wherein the system I/O controller further comprises a primary bus arbiter coupled to the DMA controller and configured to arbitrate for the local bus on behalf of the DMA agent.
Claim 5
Independent Claim
97 words
A system input/output (I/O) controller comprising: a direct memory access (DMA) controller; interface logic coupled to the DMA controller and configured to communicate over a local bus according to a local bus protocol; a plurality of control/byte enable lines coupled to the interface logic wherein the control/byte enable lines carry control and byte enable information in a time multiplexed manner; and a plurality of address lines coupled to the interface logic, including address lines that carry DMA control information from the DMA controller to a DMA agent through the interface logic, including a type of DMA cycle.
Claim 6
Independent Claim
97 words
A system input/output (I/O) controller comprising: a direct memory access (DMA) controller; interface logic coupled to the DMA controller and configured to communicate over a local bus according to a local bus protocol; a plurality of control/byte enable lines coupled to the interface logic wherein the control/byte enable lines carry control and byte enable information in a time multiplexed manner; and a plurality of address lines coupled to the interface logic, including address lines that carry DMA control information from the DMA controller to a DMA agent through the interface logic, including a type of DMA cycle.
Claim 7
Dependent Claim
32 words
The system I/O controller of claim 4, further comprising a primary bus arbiter coupled to the DMA controller and configured to arbitrate for the local bus on behalf of the DMA agent.
Claim 8
Dependent Claim
30 words
The system I/O controller of claim 4, wherein the type of DMA cycle includes: a normal read cycle; a normal write cycle; a verify cycle; and a terminal count cycle.
Claim 9
Dependent Claim
38 words
The system I/O controller of claim 4, further comprising encode/decode logic coupled to the DMA controller and configured to receive encoded requests for DMA operations from the DMA agent and to transmit grant signals to the DMA agent.
Claim 10
Independent Claim
147 words
A method for controlling direct access to a memory device of a computer system by a direct memory access (DMA) agent, comprising the steps of: receiving a DMA request over a local bus from the DMA agent according to a serial protocol; transmitting a grant signal over the local bus to the DMA agent granting the DMA request; performing a memory phase of the DMA transaction, including: transmitting address information via address/data lines of the local bus; transmitting local bus command information via control/byte enable lines of the local bus; and transferring data between the memory device and a data buffer via the address/data lines; and performing an input/output (I/O) phase of the DMA transaction, including: transmitting byte lane information via the control/byte enable lines; and transmitting a signal to convey DMA control information to the DMA agent wherein the signal is encoded on the address/data lines.
Claim 11
Independent Claim
147 words
A method for controlling direct access to a memory device of a computer system by a direct memory access (DMA) agent, comprising the steps of: receiving a DMA request over a local bus from the DMA agent according to a serial protocol; transmitting a grant signal over the local bus to the DMA agent granting the DMA request; performing a memory phase of the DMA transaction, including: transmitting address information via address/data lines of the local bus; transmitting local bus command information via control/byte enable lines of the local bus; and transferring data between the memory device and a data buffer via the address/data lines; and performing an input/output (I/O) phase of the DMA transaction, including: transmitting byte lane information via the control/byte enable lines; and transmitting a signal to convey DMA control information to the DMA agent wherein the signal is encoded on the address/data lines.
Claim 12
Dependent Claim
32 words
The method of claim 8, wherein the DMA control information comprises a DMA cycle type, including: a normal read cycle; a normal write cycle; a verify cycle; and a terminal count cycle.
References Cited (Backward Citations)
US5255376A
Cited
US5535362A
Cited
US5561783A
Cited
US5396602A
Cited
US5450551A
Cited
US5561821A
Cited
US5561819A
Cited
US5613075A
Cited
US5471590A
Cited
US5533200A
Cited
US5623700A
Cited
US5619728A
Cited
US5623691A
Cited
US5621902A
Cited
US5623697A
Cited
US5594873A
Cited
US5517650A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-16 | 2001-09-15 | 2002-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-16 | 2005-09-15 | 2006-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-16 | 2009-09-15 | 2010-03-17 | $7700.00 | Window Closed / Lapsed |