Patent DE594644C successfully refreshed from Google Patents.
US5535362A
Expired / Lapsed
US
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Data transfer control apparatus wherein a time value is compared to a clocked timer value with a comparison of the values causing the transfer of bus use right
Assignee: Mitsubishi Electric Corp
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Filing: 1993-02-04
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Granted: 1996-07-09
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Expires: 2013-02-04
Abstract
Abstract To change the priority order of a DMA transfer circuit and a CPU for the bus use right in a data processing system comprising the DMA transfer circuit, when an overflow occurs in the DMA transfer timer during DMA transfer, a request signal for shifting the bus use right from the DMA transfer circuit to the CPU is outputted to a bus use right decision circuit to suspend DMA transfer. After the bus use right is transferred from the DMA transfer circuit to the CPU, the CPU resumes operation. When an overflow occurs in the DMA transfer timer, a request signal for shifting the bus use right from the CPU to the DMA transfer circuit is outputted to the bus use right decision circuit to transfer the bus use right from the CPU to the DMA transfer circuit with the same means as the start of DMA transfer and to resume DMA transfer.
Inventors
- 👤 Yasuhiro Ami
- 👤 Takeshi Fujii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:30
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/36; G06F13/362
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
152 words
A data transfer control system comprising: a data bus; a central processing unit coupled to the data bus; a memory coupled to the data bus; a plurality of peripheral functional circuits; a DMA transfer circuit, coupled to the data bus, for transferring data between said plurality of peripheral functional circuits and said memory upon acquiring a right to use the data bus from said central processing unit in response to a DMA transfer request signal from said plurality of peripheral function circuits; and decision means for alternately selecting which of said central processing unit or said DMA transfer circuit is to be granted a bus use right and for granting, after the receipt of said DMA transfer request and during a DMA transfer cycle, said bus use right to a selected one of said central processing unit or DMA transfer circuit in every cycle time counted by means of a system clock.
Claim 2
Dependent Claim
152 words
A data transfer control system comprising: a data bus; a central processing unit coupled to the data bus; a memory coupled to the data bus; a plurality of peripheral functional circuits; a DMA transfer circuit, coupled to the data bus, for transferring data between said plurality of peripheral functional circuits and said memory upon acquiring a right to use the data bus from said central processing unit in response to a DMA transfer request signal from said plurality of peripheral function circuits; and decision means for alternately selecting which of said central processing unit or said DMA transfer circuit is to be granted a bus use right and for granting, after the receipt of said DMA transfer request and during a DMA transfer cycle, said bus use right to a selected one of said central processing unit or DMA transfer circuit in every cycle time counted by means of a system clock.
Claim 3
Dependent Claim
328 words
A data transfer control system comprising: a data bus; a central processing unit coupled to the data bus; a memory coupled to the data bus; a plurality of peripheral functional circuits; a DMA transfer circuit, coupled to the data bus, for transferring data between said plurality of peripheral functional circuits and said memory upon acquiring a right to use the data bus from said central processing unit in response to a DMA transfer request signal from said plurality of peripheral function circuits; and decision means for alternately selecting which of said central processing unit or said DMA transfer circuit is to be granted a bus use right and for granting, after the receipt of said DMA transfer request and during a DMA transfer cycle, said bus use right to a selected one of said central processing unit or DMA transfer circuit in every cycle time counted by means of a system clock; wherein said decision means comprises: a counter for counting said cycle time by means of said system clock, a timer register for setting an instruction execution time for said central processing unit or a DMA transfer cycle time for said DMA transfer circuit, a setting value for said time being supplied by an external terminal or software, a coincidence decision circuit receiving a count value counted by said counter and the value set in said timer register and outputting a coincidence signal at the time when said count value coincides with said set value, a bus use right change control circuit receiving said coincidence signal and outputting a request signal for changing said bus use right, and a bus use right decision circuit for forcing said DMA transfer circuit to acquire said bus use right by stopping the operation of said central processing unit or forcing said central processing unit to acquire said bus use right by stopping the operation of said DMA transfer circuit in response to said request signal for changing bus use right.
Claim 4
Dependent Claim
328 words
A data transfer control system comprising: a data bus; a central processing unit coupled to the data bus; a memory coupled to the data bus; a plurality of peripheral functional circuits; a DMA transfer circuit, coupled to the data bus, for transferring data between said plurality of peripheral functional circuits and said memory upon acquiring a right to use the data bus from said central processing unit in response to a DMA transfer request signal from said plurality of peripheral function circuits; and decision means for alternately selecting which of said central processing unit or said DMA transfer circuit is to be granted a bus use right and for granting, after the receipt of said DMA transfer request and during a DMA transfer cycle, said bus use right to a selected one of said central processing unit or DMA transfer circuit in every cycle time counted by means of a system clock; wherein said decision means comprises: a counter for counting said cycle time by means of said system clock, a timer register for setting an instruction execution time for said central processing unit or a DMA transfer cycle time for said DMA transfer circuit, a setting value for said time being supplied by an external terminal or software, a coincidence decision circuit receiving a count value counted by said counter and the value set in said timer register and outputting a coincidence signal at the time when said count value coincides with said set value, a bus use right change control circuit receiving said coincidence signal and outputting a request signal for changing said bus use right, and a bus use right decision circuit for forcing said DMA transfer circuit to acquire said bus use right by stopping the operation of said central processing unit or forcing said central processing unit to acquire said bus use right by stopping the operation of said DMA transfer circuit in response to said request signal for changing bus use right.
Claim 5
Dependent Claim
353 words
A data transfer control system including a data bus; a central processing unit coupled to the data bus; a memory coupled to the data bus; a plurality of peripheral functional circuits; a DMA transfer circuit, coupled to the data bus, for transferring data between said plurality of peripheral functional circuits and said memory upon acquiring a right to use the data bus from said central processing unit in response to a DMA transfer request signal from said plurality of peripheral function circuits; and decision means for alternately selecting which of said central processing unit or said DMA transfer circuit is to be granted a bus use right and for granting, after the receipt of said DMA transfer request and during a DMA transfer cycle, said bus use right to a selected one of said central processing unit or DMA transfer circuit in every cycle time counted by means of a system clock; wherein said decision means comprises: a counter for counting cycle time by means of said system clock, a first timer register for setting an execution cycle time for said central processing unit, a setting value for said time being supplied by an external terminal or software, a second timer register for setting a DMA transfer cycle time for said DMA transfer circuit, a setting value for said time being supplied by an external terminal or software, a coincidence decision circuit receiving the count value by said counter and the value set in said first timer register or in said second timer register and outputting a coincidence signal at the time when said count value coincides with said set value, a bus use right change control circuit receiving said coincidence signal and outputting a request signal for changing said bus use right, a bus use right decision circuit for forcing said DMA transfer circuit to acquire said bus use right by stopping the operation of said central processing unit or forcing said central processing unit to acquire said bus use right by stopping the operation of said DMA transfer circuit in response to said request signal for changing said bus use right.
Claim 6
Dependent Claim
353 words
A data transfer control system including a data bus; a central processing unit coupled to the data bus; a memory coupled to the data bus; a plurality of peripheral functional circuits; a DMA transfer circuit, coupled to the data bus, for transferring data between said plurality of peripheral functional circuits and said memory upon acquiring a right to use the data bus from said central processing unit in response to a DMA transfer request signal from said plurality of peripheral function circuits; and decision means for alternately selecting which of said central processing unit or said DMA transfer circuit is to be granted a bus use right and for granting, after the receipt of said DMA transfer request and during a DMA transfer cycle, said bus use right to a selected one of said central processing unit or DMA transfer circuit in every cycle time counted by means of a system clock; wherein said decision means comprises: a counter for counting cycle time by means of said system clock, a first timer register for setting an execution cycle time for said central processing unit, a setting value for said time being supplied by an external terminal or software, a second timer register for setting a DMA transfer cycle time for said DMA transfer circuit, a setting value for said time being supplied by an external terminal or software, a coincidence decision circuit receiving the count value by said counter and the value set in said first timer register or in said second timer register and outputting a coincidence signal at the time when said count value coincides with said set value, a bus use right change control circuit receiving said coincidence signal and outputting a request signal for changing said bus use right, a bus use right decision circuit for forcing said DMA transfer circuit to acquire said bus use right by stopping the operation of said central processing unit or forcing said central processing unit to acquire said bus use right by stopping the operation of said DMA transfer circuit in response to said request signal for changing said bus use right.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |