Programmable counter/timer device with programmable registers having programmable functions

Claim 2

A programmable pulse input/output processing system, comprising: a microcomputer including a central processing unit; and a programmable pulse input/output processing unit connected to said microcomputer through a system bus, said programmable pulse input/output processing unit comprising: (a) task instruction generating means for generating task instructions corresponding to pulse processing operations; (b) operation means for performing pulse processing operations, and including (a) a register group made up of a plurality of registers each being selectively programmable to perform any of a plurality of register functions necessary for said pulse processing operations, said plurality of register functions including a counter/timer function, a compare function and a capture function, such that the number of counter/timer function registers, compare function registers and capture function registers can be freely changed to control various operations of said microcomputer, (b) an arithmetic unit for performing an arithmetic/logic operation on the basis of data from said register group, and (c) bus means for transferring data between said register group and said arithmetic unit; (c) interface bus means for transferring data between said register group and said central processing unit through said system bus; and (d) task instruction control means connected to said task instruction generating means and said operation means, and being responsive to a task instruction generated by said task instruction generating means, for specifying at least one of said plurality of registers included in said register group of said operation means to be used for a particular pulse processing operation, and for causing said arithmetic unit to perform an arithmetic/logic operation corresponding to said task instruction on the basis of data contained in said at least one of said plurality of registers.

Claim 3

A microcomputer chip comprising: a central processing unit, and a pulse input/output processing unit connected to said central processing unit, said pulse input/output processing unit comprising: a plurality of I/O terminal pins for receiving signals from and sending signals to said central processing unit; task instruction generating means for generating task instructions specifying counter/timer operations, registers to be used in performing said counter/timer operations and I/O terminal pins to be employed in receiving signals from and sending signals to said central processing unit in performing said counter/timer operations; counter/timer operation means coupled to said I/O terminal pins for performing counter/timer operations including (a) a register group made up of a plurality of registers each being selectively programmable to perform any of a plurality of register functions necessary for said counter/timer operations, said plurality of register functions including a counter/timer function, a compare function and a capture function such that the number of counter/timer function registers, compare function registers and capture function registers can be changed to accommodate various counter/timer operations, (b) arithmetic unit means for performing an arithmetic/logic operation on the basis of data from said register group, and (c) bus means for transferring data between said register group and said arithmetic unit means; and task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to a task instruction generated by said task instruction generating means, for specifying (i) at least one I/O terminal pin for receipt of signals from or for supplying signals to said control processing unit and (ii) at least one of said plurality of registers included in said register group of said counter/timer operations means to be used for a particular counter/timer operation which is responsive to a signal received on said specified I/O terminal pin or which supplies a resultant signal to said specified I/O terminal pin, and for causing said arithmetic unit means to perform an arithmetic/logic operation corresponding to said particular counter/timer operation specified by said task instruction on the basis of data contained in said at least one of said plurality of registers.

Claim 4

A microcomputer chip comprising: a central processing unit, and a pulse input/output processing unit connected to said central processing unit, said pulse input/output processing unit comprising: a plurality of I/O terminal pins for receiving signals from and sending signals to said central processing unit; task instruction generating means for generating task instructions specifying counter/timer operations, registers to be used in performing said counter/timer operations and I/O terminal pins to be employed in receiving signals from and sending signals to said central processing unit in performing said counter/timer operations; counter/timer operation means coupled to said I/O terminal pins for performing counter/timer operations including (a) a register group made up of a plurality of registers each being selectively programmable to perform any of a plurality of register functions necessary for said counter/timer operations, said plurality of register functions including a counter/timer function, a compare function and a capture function such that the number of counter/timer function registers, compare function registers and capture function registers can be changed to accommodate various counter/timer operations, (b) arithmetic unit means for performing an arithmetic/logic operation on the basis of data from said register group, and (c) bus means for transferring data between said register group and said arithmetic unit means; and task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to a task instruction generated by said task instruction generating means, for specifying (i) at least one I/O terminal pin for receipt of signals from or for supplying signals to said control processing unit and (ii) at least one of said plurality of registers included in said register group of said counter/timer operations means to be used for a particular counter/timer operation which is responsive to a signal received on said specified I/O terminal pin or which supplies a resultant signal to said specified I/O terminal pin, and for causing said arithmetic unit means to perform an arithmetic/logic operation corresponding to said particular counter/timer operation specified by said task instruction on the basis of data contained in said at least one of said plurality of registers.

Claim 5

A microcomputer chip comprising: a central processing unit, and a pulse input/output processing unit connected to said central processing unit, said pulse input/output processing unit comprising: a plurality of I/O terminal pins for receiving signals from and sending signals to an external device; task instruction generating means for successively generating task instructions specifying counter/timer operations, registers to be used in performing said counter/timer operations and I/O terminal pins to be employed in receiving signals from and sending signals to said external device in performing said counter/timer operations; counter/timer operation means coupled to said I/O terminal pins for performing counter/timer operations including (a) a register group made up of a plurality of registers each being selectively programmable to perform any of a plurality of register functions necessary for said computer/timer operations, said plurality of register functions including a counter/timer function, a compare function and a capture function such that the number of counter/timer function registers, compare function registers and capture function registers can be changed to accommodate various counter/timer operations, (b) arithmetic unit means for performing an arithmetic/logic operation on the basis of data from said register group, and (c) bus means for transferring data between said register group and said arithmetic unit means; and task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to a task instruction generated by said task instruction generating means, for specifying (i) at least one I/O terminal pin for receipt of signals from or for supplying signals to said external device and (ii) at least one of said plurality of registers included in said register group of said counter/timer operation means to be used for a particular counter/timer operation which is responsive to a signal received on said specified i/o terminal pin or which supplies a resultant signal to said specified I/O terminal pin, and for causing said arithmetic unit means to perform an arithmetic/logic operation corresponding to said particular counter/timer operation specified by said task instruction on the basis of data contained in said at least one of said plurality of registers.

Claim 6

A microcomputer chip comprising: a central processing unit, and a pulse input/output processing unit connected to said central processing unit, said pulse input/output processing unit comprising: a plurality of I/O terminal pins for receiving signals from and sending signals to an external device; task instruction generating means for successively generating task instructions specifying counter/timer operations, registers to be used in performing said counter/timer operations and I/O terminal pins to be employed in receiving signals from and sending signals to said external device in performing said counter/timer operations; counter/timer operation means coupled to said I/O terminal pins for performing counter/timer operations including (a) a register group made up of a plurality of registers each being selectively programmable to perform any of a plurality of register functions necessary for said computer/timer operations, said plurality of register functions including a counter/timer function, a compare function and a capture function such that the number of counter/timer function registers, compare function registers and capture function registers can be changed to accommodate various counter/timer operations, (b) arithmetic unit means for performing an arithmetic/logic operation on the basis of data from said register group, and (c) bus means for transferring data between said register group and said arithmetic unit means; and task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to a task instruction generated by said task instruction generating means, for specifying (i) at least one I/O terminal pin for receipt of signals from or for supplying signals to said external device and (ii) at least one of said plurality of registers included in said register group of said counter/timer operation means to be used for a particular counter/timer operation which is responsive to a signal received on said specified i/o terminal pin or which supplies a resultant signal to said specified I/O terminal pin, and for causing said arithmetic unit means to perform an arithmetic/logic operation corresponding to said particular counter/timer operation specified by said task instruction on the basis of data contained in said at least one of said plurality of registers.

Claim 7

A microcomputer chip comprising: a central processing unit, and a pulse input/output processing unit connected to said central processing unit, said pulse input/output processing unit comprising: a plurality of I/O terminal pins for receiving signals from and sending signals to an external device; task instruction generating means for generating a task instruction which specifies (1) an input counter/timer operation, (2) a first register to serve as a counter/timer register, (3) a second register to serve as a capture register, (4) a first I/O terminal pin for receipt of a clock signal from said external device and (5 ) a second I/O terminal pin for receipt of a capture signal from said external device; counter/timer operation means coupled to said I/O terminal pins for performing counter/timer operations including (a) a plurality of registers selectable in accordance with said task instruction for performing selected register functions necessary for said counter/timer operations, (b) arithmetic unit means for performing an arithmetic/logic operation on data from a selected register or registers, and (c) bus means for transferring data between said registers and said arithmetic unit means; and task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to said task instruction generated by said task instruction generating means, (i) for specifying a first one of said plurality of registers to serve as a counter/timer register and a second one of said registers to serve as a capture register such that the counter/timer register and the capture function register can be selected by said task instruction control means to accommodate various counter/timer operations, (ii) for controlling said arithmetic unit means to count clock signals receiving on said first I/O terminal pin specified by said task instruction and to store said count in said first register, and (iii) for controlling said first and second register to transfer a count in said first registers to said second register in response to receipt of a capture signal on said second I/O terminal pin specified by said task instruction.

Claim 8

A microcomputer chip comprising: a central processing unit, and a pulse input/output processing unit connected to said central processing unit, said pulse input/output processing unit comprising: a plurality of I/O terminal pins for receiving signals from and sending signals to an external device; task instruction generating means for generating a task instruction which specifies (1) an input counter/timer operation, (2) a first register to serve as a counter/timer register, (3) a second register to serve as a capture register, (4) a first I/O terminal pin for receipt of a clock signal from said external device and (5 ) a second I/O terminal pin for receipt of a capture signal from said external device; counter/timer operation means coupled to said I/O terminal pins for performing counter/timer operations including (a) a plurality of registers selectable in accordance with said task instruction for performing selected register functions necessary for said counter/timer operations, (b) arithmetic unit means for performing an arithmetic/logic operation on data from a selected register or registers, and (c) bus means for transferring data between said registers and said arithmetic unit means; and task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to said task instruction generated by said task instruction generating means, (i) for specifying a first one of said plurality of registers to serve as a counter/timer register and a second one of said registers to serve as a capture register such that the counter/timer register and the capture function register can be selected by said task instruction control means to accommodate various counter/timer operations, (ii) for controlling said arithmetic unit means to count clock signals receiving on said first I/O terminal pin specified by said task instruction and to store said count in said first register, and (iii) for controlling said first and second register to transfer a count in said first registers to said second register in response to receipt of a capture signal on said second I/O terminal pin specified by said task instruction.

Claim 9

A microcomputer chip comprising: a central processing unit, and a pulse input/output processing unit connected to said central processing unit, said pulse input/output processing unit comprising: a plurality of I/O terminal pins for receiving signals from and sending signals to an external device; task instruction generating means for generating a task instruction which specifies (1) an input counter/timer operation, (2) a first register to serve as a counter/timer register, (3) a second register to serve as a compare register, and (4) a first I/O terminal pin for sending an output signal to said external device; counter/timer operation means coupled to said I/O terminal pins for performing counter/timer operations including (a) a plurality of registers selectable in accordance with said task instruction for performing selected register functions necessary for said counter/timer operations, (b) arithmetic unit means for performing an arithmetic/logic operation on data from a selected register or registers, and (c) bus means for transferring data between said registers and said arithmetic unit means; and task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to said task instruction generated by said task instruction generating means, (i) for specifying a first one of said plurality of registers to serve as a counter/timer register and a second one of said registers to serve as a compare register such that the counter/timer register and the compare function register can be selected by said task instruction means to accommodate various counter/timer operations, (ii) for controlling said arithmetic unit means to periodically increment a value stored in said first register, (iii) for comparing the contents of said first register with a value stored in said second register, and (iv) applying an output signal to said first I/O first pin specified by said task instruction when coincidence is detected between the contents of said first and second registers.

Claim 10

A microcomputer chip comprising: a central processing unit, and a pulse input/output processing unit connected to said central processing unit, said pulse input/output processing unit comprising: a plurality of I/O terminal pins for receiving signals from and sending signals to an external device; task instruction generating means for generating a task instruction which specifies (1) an input counter/timer operation, (2) a first register to serve as a counter/timer register, (3) a second register to serve as a compare register, and (4) a first I/O terminal pin for sending an output signal to said external device; counter/timer operation means coupled to said I/O terminal pins for performing counter/timer operations including (a) a plurality of registers selectable in accordance with said task instruction for performing selected register functions necessary for said counter/timer operations, (b) arithmetic unit means for performing an arithmetic/logic operation on data from a selected register or registers, and (c) bus means for transferring data between said registers and said arithmetic unit means; and task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to said task instruction generated by said task instruction generating means, (i) for specifying a first one of said plurality of registers to serve as a counter/timer register and a second one of said registers to serve as a compare register such that the counter/timer register and the compare function register can be selected by said task instruction means to accommodate various counter/timer operations, (ii) for controlling said arithmetic unit means to periodically increment a value stored in said first register, (iii) for comparing the contents of said first register with a value stored in said second register, and (iv) applying an output signal to said first I/O first pin specified by said task instruction when coincidence is detected between the contents of said first and second registers.

Claim 11

A microcomputer chip comprising: a central processing unit, and a programmable pulse input/output processing unit connected to said central processing unit, said programmable pulse input/output processing unit comprising: (A) task instruction generating means for generating a plurality of task instructions corresponding to counter/timer operations; (B) counter/timer operation means for performing counter/timer operations and including (a) a register group made up of a plurality of registers each being selectively programmable to perform any of a plurality of register functions necessary for said counter/timer operations, said plurality of register functions including a counter/timer function, a compare function, and a capture function, such that the number of counter/timer registers, compare function registers and capture function registers can be changed to control various operations of said programmable pulse input/output processing unit, (b) arithmetic unit means for performing an arithmetic/logic operation on the basis of data from said register group, and (c) bus means for transferring data between said register group and said arithmetic unit means; (C) interface bus means for transferring data between said group and said central processing unit through said data bus; and (D) task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to a task instruction generated by said task instruction generating means, for specifying at least one of said plurality of registers included in said register group of said counter/timer operation means to be used for a particular counter/timer operation, and for causing said arithmetic unit means to perform an arithmetic/logic operation corresponding to said task instruction on the basis of data contained in said at least one of said plurality of registers.

Claim 12

A microcomputer chip comprising: a central processing unit, and a programmable pulse input/output processing unit connected to said central processing unit, said programmable pulse input/output processing unit comprising: (A) task instruction generating means for generating a plurality of task instructions corresponding to counter/timer operations; (B) counter/timer operation means for performing counter/timer operations and including (a) a register group made up of a plurality of registers each being selectively programmable to perform any of a plurality of register functions necessary for said counter/timer operations, said plurality of register functions including a counter/timer function, a compare function, and a capture function, such that the number of counter/timer registers, compare function registers and capture function registers can be changed to control various operations of said programmable pulse input/output processing unit, (b) arithmetic unit means for performing an arithmetic/logic operation on the basis of data from said register group, and (c) bus means for transferring data between said register group and said arithmetic unit means; (C) interface bus means for transferring data between said group and said central processing unit through said data bus; and (D) task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to a task instruction generated by said task instruction generating means, for specifying at least one of said plurality of registers included in said register group of said counter/timer operation means to be used for a particular counter/timer operation, and for causing said arithmetic unit means to perform an arithmetic/logic operation corresponding to said task instruction on the basis of data contained in said at least one of said plurality of registers.

Claim 13

A microprocessor comprising: a central processing unit, and a programmable pulse input/output processing unit connected to said central processing unit, said programmable pulse input/output processing unit comprising: (A) task instruction generating means for generating a plurality of task instructions corresponding to counter/timer operations; (B) counter/timer operation means for performing counter/timer operations and including (a) a register group made up of a plurality of registers each being selectively programmable to perform any of a plurality of register functions necessary for said counter/timer operations, said plurality of register functions including a counter/timer function, a compare function, and a capture function, such that the number of counter/timer registers, compare function registers and capture function registers can be changed to control various operations of said programmable pulse input/output processing unit, (b) arithmetic unit means for performing an arithmetic/logic operation on the basis of data from said register group, and (c) bus means for transferring data between said register group and said arithmetic unit means; (C) interface bus means for transferring data between said group and said central processing unit through said data bus; and (D) task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to a task instruction generated by said task instruction generating means, for specifying at least one of said plurality of registers included in said register group of said counter/timer operation means to be used for a particular counter/timer operation, and for causing said arithmetic unit means to perform an arithmetic/logic operation corresponding to said task instruction on the basis of data contained in said at least one of said plurality of registers.

Claim 14

A microprocessor comprising: a central processing unit, and a programmable pulse input/output processing unit connected to said central processing unit, said programmable pulse input/output processing unit comprising: (A) task instruction generating means for generating a plurality of task instructions corresponding to counter/timer operations; (B) counter/timer operation means for performing counter/timer operations and including (a) a register group made up of a plurality of registers each being selectively programmable to perform any of a plurality of register functions necessary for said counter/timer operations, said plurality of register functions including a counter/timer function, a compare function, and a capture function, such that the number of counter/timer registers, compare function registers and capture function registers can be changed to control various operations of said programmable pulse input/output processing unit, (b) arithmetic unit means for performing an arithmetic/logic operation on the basis of data from said register group, and (c) bus means for transferring data between said register group and said arithmetic unit means; (C) interface bus means for transferring data between said group and said central processing unit through said data bus; and (D) task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to a task instruction generated by said task instruction generating means, for specifying at least one of said plurality of registers included in said register group of said counter/timer operation means to be used for a particular counter/timer operation, and for causing said arithmetic unit means to perform an arithmetic/logic operation corresponding to said task instruction on the basis of data contained in said at least one of said plurality of registers.

Claim 15

A counter/timer device for use with a microcomputer to perform counter/timer operations for said microcomputer, comprising: a plurality of I/O terminal pins for receiving signals from and sending signals to said microcomputer; task instruction generating means for generating task instructions specifying counter/timer operations and registers to be used in performing said counter/timer operations; counter/timer operation means coupled to said I/O terminal pins for performing counter/timer operations including (a) a register group made up of a plurality of registers each being selectively programmable to perform any of a plurality of register functions necessary for said counter/timer operations, said plurality of register functions including a counter/timer function, a compare function and a capture function, such that the number of counter/timer function registers, compare function registers and capture function registers can be freely changed to accommodate various counter/timer operations, (b) an arithmetic unit for performing an arithmetic/logic operation on the basis of data from said register group, and (c) bus means for transferring data between said register group and said arithmetic unit; and task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to a task instruction generated by said task instruction generating means, for specifying (i) at least one I/O terminal pin for receipt of signals from or for supplying signals to said microcomputer, and (ii) at least one of said plurality of registers included in said register group of said counter/timer operation means to be used for a particular counter/timer operation which is responsive to a signal received on said specified I/O terminal pin or which supplies a resultant signal to said specified I/O terminal pin, and for causing said arithmetic unit to perform an arithmetic logic operation corresponding to said particular counter/timer operation specified by said task instruction on the basis of data contained in said at least one of said plurality of registers.

Claim 16

A counter/timer device for use with a microcomputer to perform counter/timer operations for said microcomputer, comprising: a plurality of I/O terminal pins for receiving signals from and sending signals to said microcomputer; task instruction generating means for generating task instructions specifying counter/timer operations and registers to be used in performing said counter/timer operations; counter/timer operation means coupled to said I/O terminal pins for performing counter/timer operations including (a) a register group made up of a plurality of registers each being selectively programmable to perform any of a plurality of register functions necessary for said counter/timer operations, said plurality of register functions including a counter/timer function, a compare function and a capture function, such that the number of counter/timer function registers, compare function registers and capture function registers can be freely changed to accommodate various counter/timer operations, (b) an arithmetic unit for performing an arithmetic/logic operation on the basis of data from said register group, and (c) bus means for transferring data between said register group and said arithmetic unit; and task instruction control means connected to said task instruction generating means and said counter/timer operation means, and being responsive to a task instruction generated by said task instruction generating means, for specifying (i) at least one I/O terminal pin for receipt of signals from or for supplying signals to said microcomputer, and (ii) at least one of said plurality of registers included in said register group of said counter/timer operation means to be used for a particular counter/timer operation which is responsive to a signal received on said specified I/O terminal pin or which supplies a resultant signal to said specified I/O terminal pin, and for causing said arithmetic unit to perform an arithmetic logic operation corresponding to said particular counter/timer operation specified by said task instruction on the basis of data contained in said at least one of said plurality of registers.