US4618968A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output compare system and method automatically controlilng multiple outputs in a data processor
Assignee: Motorola Solutions Inc
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Filing: 1983-11-04
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Granted: 1986-10-21
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Expires: 2003-11-04
Abstract
Abstract An output compare system and method for automatically controlling multiple outputs in a data processor includes an output compare mask register for holding a set bit therein. An output compare data register is coupled to a control output of the output compare mask register for holding a data bit therein. Apparatus for initiating an output compare function are coupled to a control input to the output compare mask register whereby the data bit will be transferred to an output of the data processor if the set bit is present. The system and method allow for simultaneous utilization of multiple output compare functions to achieve one-cycle-wide pulses on a timer output pin.
Inventors
- 👤 James M. Sibigtroth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:50
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4825; G06F1/00; G06F1/04; G06F1/14
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
178 words
In a timer system comprising: a first counter for counting pulses of a first input signal; a first compare register for selectively storing a first compare value therein; and a first comparator, coupled to the output of the first counter and to output of the first compare register, for comparing the first counter value to the first compare value, and for providing a first compare signal when said values are the same; the improvement comprising: a data register for selectively storing first and second data bits therein; a mask register for selectively storing first and second mask bits therein; and logic means, connected to said first comparator to receive the first compare signal, for providing a first output signal indicative of the state of the first data bit in response to said first compare signal only if the first mask bit is a predetermined state, and to provide a second output signal indicative of the state of the second data bit in response to said first compare signal only if the second mask bit is a predetermined state.
Claim 2
Dependent Claim
178 words
In a timer system comprising: a first counter for counting pulses of a first input signal; a first compare register for selectively storing a first compare value therein; and a first comparator, coupled to the output of the first counter and to output of the first compare register, for comparing the first counter value to the first compare value, and for providing a first compare signal when said values are the same; the improvement comprising: a data register for selectively storing first and second data bits therein; a mask register for selectively storing first and second mask bits therein; and logic means, connected to said first comparator to receive the first compare signal, for providing a first output signal indicative of the state of the first data bit in response to said first compare signal only if the first mask bit is a predetermined state, and to provide a second output signal indicative of the state of the second data bit in response to said first compare signal only if the second mask bit is a predetermined state.
Claim 3
Dependent Claim
157 words
The timer system of claim 1 further comprising: a second counter for counting pulses of a second input signal; a second compare register for selectively storing a second count value therein; and a second comparator, coupled to the output of the second counter and to the output of the second compare register, for comparing the second counter value to the second compare value, and for providing a second compare signal when said values are the same; wherein the logic means and responsive to both the first and second compare signals to provide the first output signal indicative of the state of the first data bit in response to either of said compare signals only if the first mask bit is a predetermined state, and to provide the second output signal indicative of the state of the second data bit in response to either of said compare signals only if the second mask bit is a predetermined state.
Claim 4
Dependent Claim
130 words
In a timer method comprising the steps of: counting pulses of a first input signal; selectively storing a first compare value; and comparing the first count value to the first compare value, and providing a first compare signal when said values are the same; the improvement comprising the steps of: selectively storing a first and a second data bit and a first and a second mask bit; and providing a first output signal indicative of the state of the first data bit in response to said first compare signal only if the first mask bit is a predetermined state, and providing a second output signal indicative of the state of the second data bit in response to said first compare signal only if the second mask bit is predetermined state.
Claim 5
Dependent Claim
130 words
In a timer method comprising the steps of: counting pulses of a first input signal; selectively storing a first compare value; and comparing the first count value to the first compare value, and providing a first compare signal when said values are the same; the improvement comprising the steps of: selectively storing a first and a second data bit and a first and a second mask bit; and providing a first output signal indicative of the state of the first data bit in response to said first compare signal only if the first mask bit is a predetermined state, and providing a second output signal indicative of the state of the second data bit in response to said first compare signal only if the second mask bit is predetermined state.
Claim 6
Dependent Claim
122 words
The timer method of claim 3 further comprising the steps of: counting pulses of a second input signal and providing a second count value; selectively storing a second compare signal; and comparing the second count value to the second compare value, and providing a second compare signal when said second values are the same; wherein the first output signal indicative of the state of the first data bit is provided in response to either of said compare signals only if the first mask bit is a predetermined state, and the second output signal indicative of the sate of the second data bit is provided in response to either of said compare signal only if the second mask bit is a predetermined state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-20 | 1990-04-21 | 1990-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-20 | 1994-04-21 | 1994-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-20 | 1998-04-21 | 1998-10-21 | $7700.00 | Window Closed / Lapsed |