US5561783A
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US
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Dynamic cache coherency method and apparatus using both write-back and write-through operations
Assignee: Intel Corp
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Filing: 1995-03-22
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Granted: 1996-10-01
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Expires: 2015-03-22
Abstract
Abstract A dynamic cache coherency method and apparatus providing enhanced microprocessor system performance are described. The method and apparatus are advantageously utilized in a microprocessor system comprising a central processing unit (CPU), a write back cache memory, dynamic random access memory (DRAM) main memory, a cache and DRAM controller (CDC), and a data path unit (DPU) with a write buffer. In accordance with the method of operation, following a write access by the CPU, the CDC determines whether the write buffer is full and whether the cache line associated with this access has been modified, i.e. is "clean" or "dirty." In the event that the write buffer is full, or the cache line is dirty, the write operation proceeds in accordance with a write back mode of operation. However, if the write buffer in the DPU is not full, and the cache line is clean, the CDC writes the write data to both the cache line in cache memory, and the write buffer in the DPU. These two write operations proceed concurrently, and are completed in the same amount of time. When they are completed, the processor cycle is also complete, and the CPU proceeds with its next task. Thereafter, in the background, the posted data in the write buffer is flushed to DRAM, without incurring any CPU overhead.
Inventors
- 👤 Subbarao Vanka
- 👤 Prasanna Rupasinghe
- 👤 Mark Lalich
- 👤 Abid Ahmad
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:11
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
124 words
A processor system comprising: a processor; a main memory; a cache memory coupled to the processor, the cache memory including a plurality of cache lines associated with cached addresses of the main memory; a data path unit coupled to the processor and the main memory, the data path unit further comprising at least one write buffer; a controller coupled to the processor, the cache memory, the data path unit, and the main memory, wherein the controller selects between one of a write back mode of operation and a write through mode of operation when transferring data from the processor to the main memory in accordance with a first predesignated condition of the write buffer and a selected predesignated condition of a selected cache line.
Claim 2
Dependent Claim
124 words
A processor system comprising: a processor; a main memory; a cache memory coupled to the processor, the cache memory including a plurality of cache lines associated with cached addresses of the main memory; a data path unit coupled to the processor and the main memory, the data path unit further comprising at least one write buffer; a controller coupled to the processor, the cache memory, the data path unit, and the main memory, wherein the controller selects between one of a write back mode of operation and a write through mode of operation when transferring data from the processor to the main memory in accordance with a first predesignated condition of the write buffer and a selected predesignated condition of a selected cache line.
Claim 3
Dependent Claim
60 words
The processor system of claim 1 wherein the controller selects a write back mode of operation to write data from the processor to the selected cache line in cache memory if the write buffer is full or the selected cache line contains modified data, wherein the writing of data from the selected cache line to the main memory is deferred.
Claim 4
Dependent Claim
69 words
The processor system of claim 1 wherein the controller selects a write through mode of operation to write data from the processor to both the selected cache line and to the write buffer if the write buffer is not full and the selected cache line does not contain modified data, wherein the writing of data from the write buffer to the main memory occurs during a subsequent processor cycle.
Claim 5
Independent Claim
156 words
A method of maintaining coherency between a processor cache memory and a main memory, comprising the steps of: a) initiating a write operation to transfer write data from a processor to a first address within the main memory, the processor coupled to at least one write buffer for transferring data between the processor and the main memory, the processor coupled to a controller for controller data transfer between the processor and the main memory and between the processor and the cache memory, wherein the first address is associated with a cache line within the cache memory; b) determining whether the write buffer is in a first predesignated condition; c) determining whether the cache line is in a second predesignated condition; d) performing a write-back operation if either one of the first and the second predesignated conditions is met; and e) performing a write-through operation if neither of the first and the second predesignated conditions is met.
Claim 6
Independent Claim
156 words
A method of maintaining coherency between a processor cache memory and a main memory, comprising the steps of: a) initiating a write operation to transfer write data from a processor to a first address within the main memory, the processor coupled to at least one write buffer for transferring data between the processor and the main memory, the processor coupled to a controller for controller data transfer between the processor and the main memory and between the processor and the cache memory, wherein the first address is associated with a cache line within the cache memory; b) determining whether the write buffer is in a first predesignated condition; c) determining whether the cache line is in a second predesignated condition; d) performing a write-back operation if either one of the first and the second predesignated conditions is met; and e) performing a write-through operation if neither of the first and the second predesignated conditions is met.
Claim 7
Dependent Claim
17 words
The method of claim 4 wherein the first predesignated condition is that the write buffer is full.
Claim 8
Dependent Claim
18 words
The method of claim 4 wherein the second predesignated condition is that the cache line contains modified data.
Claim 9
Dependent Claim
51 words
The method of claim 4 wherein step d) further comprises the steps of: i) using the controller to write the write data from the processor to the cache line in the cache memory; and ii) deferring a write operation from the cache line to the first address within the main memory.
Claim 10
Dependent Claim
61 words
The method of claim 4 wherein step e) further comprises the steps of: i) using the controller to write the write data from the processor to both the cache line in cache memory and to the write buffer; and ii) writing the write data from the write buffer to the first address within the main memory during a subsequent processor cycle.
Claim 11
Dependent Claim
14 words
The method of claim 4 wherein steps b) and c) are performed substantially concurrently.
Claim 12
Dependent Claim
305 words
A dynamic cache coherency method in a microprocessor system comprising a central processing unit (CPU), a cache memory coupled to said CPU having cache lines associated with addresses in said microprocessor system, main memory means, write buffer means coupled to said main memory means, and a cache and main memory controller for controlling the operation of said cache memory and controlling transfers of data from said CPU to said main memory means and said cache memory, as well as from said write buffer means to said main memory means, wherein said cache and main memory controller is coupled to said CPU, said main memory means, said cache memory, and said write buffer means, said dynamic cache coherency method comprising the steps of: said CPU initiating a write access of said data to a first address in said microprocessor system; when said write access is initiated, said cache and main memory controller determining whether said write buffer means is full and whether a particular cache line in said cache memory associated with said first address is dirty; if said write buffer means is full, said cache and main memory controller causing said data to be transferred to said particular cache line in said cache memory; if said write buffer means is not full and said particular cache line is dirty, said cache and main memory controller causing said data to be transferred to said particular cache ine in said cache memory; if said write buffer means is not full and said particular cache line is clean, said cache and main memory controller causing said data to be transferred to said particular cache line in said cache memory and said write buffer means, and thereafter, said cache and main memory controller causing said data to be transferred from said write buffer means to said main memory means.
Claim 13
Dependent Claim
305 words
A dynamic cache coherency method in a microprocessor system comprising a central processing unit (CPU), a cache memory coupled to said CPU having cache lines associated with addresses in said microprocessor system, main memory means, write buffer means coupled to said main memory means, and a cache and main memory controller for controlling the operation of said cache memory and controlling transfers of data from said CPU to said main memory means and said cache memory, as well as from said write buffer means to said main memory means, wherein said cache and main memory controller is coupled to said CPU, said main memory means, said cache memory, and said write buffer means, said dynamic cache coherency method comprising the steps of: said CPU initiating a write access of said data to a first address in said microprocessor system; when said write access is initiated, said cache and main memory controller determining whether said write buffer means is full and whether a particular cache line in said cache memory associated with said first address is dirty; if said write buffer means is full, said cache and main memory controller causing said data to be transferred to said particular cache line in said cache memory; if said write buffer means is not full and said particular cache line is dirty, said cache and main memory controller causing said data to be transferred to said particular cache ine in said cache memory; if said write buffer means is not full and said particular cache line is clean, said cache and main memory controller causing said data to be transferred to said particular cache line in said cache memory and said write buffer means, and thereafter, said cache and main memory controller causing said data to be transferred from said write buffer means to said main memory means.
Claim 14
Dependent Claim
20 words
The dynamic cache coherency as provided in claim 10, wherein said main memory comprises a dynamic random access memory (DRAM).
Claim 15
Dependent Claim
74 words
The dynamic cathe coherency method as provided in claim 10, wherein, subsequent to said step of, if said write buffer is full, said cache and main meomry controller causing said data to be transferred to said particular cache line in said cache memory, said data is written back from said particular cache line in said cache memory to said main memory means when the data has not been updated in the main memory means.
Claim 16
Dependent Claim
82 words
The dynamic cache coherency method as provided in claim 12, wherein, subsequent to said step of, if said write buffer is not full and said particular cache line is dirty, said cache and main memory controller causing said data to be transferred to said particular cache line in said cache memory, said data is written back from said particular cache line in said cache memory to said main memory means when the data has not been updated in the main memory means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-01 | 2000-04-01 | 2000-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-01 | 2004-04-01 | 2004-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-01 | 2008-04-01 | 2008-10-01 | $7700.00 | Window Closed / Lapsed |