US5469555A
Expired / Lapsed
US
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Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system
Assignee: OPTI Inc A CORP OF
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Filing: 1992-05-28
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Granted: 1995-11-21
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Expires: 2012-05-28
Abstract
Abstract Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.
Inventors
- 👤 Subir K. Ghosh
- 👤 Dipankar Bhattacharya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:24
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0888; G06F12/0891; G06F12/0215
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
245 words
A method for managing a memory subsystem in a computer system, the memory subsystem including a secondary memory, a cache memory and memory subsystem control apparatus, said method being for use in response to a plurality of cache hit data write accesses each occurring at a different access time, said method comprising the steps of, in response to each given one of said cache hit data write accesses: determining whether said memory subsystem is, at the time of said given write access, in a first state in which said control apparatus can write the data of said given write access to said secondary memory within a first length of time after the time of said given write access, or in a second state in which said control apparatus requires longer than said first length of time to write the data of said given write access to said secondary memory, said memory subsystem being in said first state for some of said write accesses and in said second state for others of said write accesses; writing the data of said given write access to said memory subsystem using a first cache write policy if said memory subsystem is in said first state at the time of said given write access; and writing the data of said given write access to said memory subsystem using a second cache write policy if said memory subsystem is in said second state at the time of said given write access.
Claim 2
Independent Claim
245 words
A method for managing a memory subsystem in a computer system, the memory subsystem including a secondary memory, a cache memory and memory subsystem control apparatus, said method being for use in response to a plurality of cache hit data write accesses each occurring at a different access time, said method comprising the steps of, in response to each given one of said cache hit data write accesses: determining whether said memory subsystem is, at the time of said given write access, in a first state in which said control apparatus can write the data of said given write access to said secondary memory within a first length of time after the time of said given write access, or in a second state in which said control apparatus requires longer than said first length of time to write the data of said given write access to said secondary memory, said memory subsystem being in said first state for some of said write accesses and in said second state for others of said write accesses; writing the data of said given write access to said memory subsystem using a first cache write policy if said memory subsystem is in said first state at the time of said given write access; and writing the data of said given write access to said memory subsystem using a second cache write policy if said memory subsystem is in said second state at the time of said given write access.
Claim 3
Dependent Claim
31 words
The method as defined in claim 1, wherein the first cache write policy is a write-through cache write policy and the second cache write policy is a write-back cache write policy.
Claim 4
Dependent Claim
241 words
Memory management apparatus for managing a memory subsystem in a computer system, the memory subsystem including a secondary memory and a cache memory, said apparatus being for use in response to a plurality of cache hit data write accesses each occurring at a different access time, said apparatus comprising: memory subsystem control apparatus having first and second states, said first state being a state in which said memory subsystem control apparatus can write the data of one of said write accesses to said secondary memory within a first length of time after the time of the write access, and said second state being a state in which said memory subsystem control apparatus requires longer than said first length of time to write the data of the write access to said secondary memory, said memory subsystem control apparatus being in said first state for some of said write accesses and in said second state for others of said write accesses; means for writing the data of each given one of said write accesses to said memory subsystem using a first cache write policy if said memory subsystem control apparatus is in said first state at the time of said given write access; and means for writing the data of said given write access to said memory subsystem using a second cache write policy if said memory subsystem control apparatus is in said second state at the time of said given write access.
Claim 5
Dependent Claim
241 words
Memory management apparatus for managing a memory subsystem in a computer system, the memory subsystem including a secondary memory and a cache memory, said apparatus being for use in response to a plurality of cache hit data write accesses each occurring at a different access time, said apparatus comprising: memory subsystem control apparatus having first and second states, said first state being a state in which said memory subsystem control apparatus can write the data of one of said write accesses to said secondary memory within a first length of time after the time of the write access, and said second state being a state in which said memory subsystem control apparatus requires longer than said first length of time to write the data of the write access to said secondary memory, said memory subsystem control apparatus being in said first state for some of said write accesses and in said second state for others of said write accesses; means for writing the data of each given one of said write accesses to said memory subsystem using a first cache write policy if said memory subsystem control apparatus is in said first state at the time of said given write access; and means for writing the data of said given write access to said memory subsystem using a second cache write policy if said memory subsystem control apparatus is in said second state at the time of said given write access.
Claim 6
Dependent Claim
31 words
The method as defined in claim 3, wherein said first cache write policy is a write-through cache write policy and said second cache write policy is a write-back cache write policy.
Claim 7
Independent Claim
104 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, comprising the steps of: determining whether said cache hit write access is also a DRAM page hit write access; writing said data to said memory subsystem using a write-through policy only if said cache hit write access is also a DRAM page hit write access; and writing said data to said memory subsystem using a writeback policy if said cache hit write access is not also a DRAM page hit write access.
Claim 8
Independent Claim
104 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, comprising the steps of: determining whether said cache hit write access is also a DRAM page hit write access; writing said data to said memory subsystem using a write-through policy only if said cache hit write access is also a DRAM page hit write access; and writing said data to said memory subsystem using a writeback policy if said cache hit write access is not also a DRAM page hit write access.
Claim 9
Independent Claim
158 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; writing said data to said memory subsystem using a write-through policy only if said cache hit write access is also a DRAM page hit write access and said RAS# signal is active; writing said data to said memory subsystem using a write-back policy if said cache hit write access is not also a DRAM page hit write access; and writing said data to said memory subsystem using a write-back policy also if said RAS# signal is inactive.
Claim 10
Independent Claim
158 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; writing said data to said memory subsystem using a write-through policy only if said cache hit write access is also a DRAM page hit write access and said RAS# signal is active; writing said data to said memory subsystem using a write-back policy if said cache hit write access is not also a DRAM page hit write access; and writing said data to said memory subsystem using a write-back policy also if said RAS# signal is inactive.
Claim 11
Independent Claim
194 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; determining whether a refresh of said DRAM is pending; writing said data to said memory subsystem using a write-through policy only if said cache hit write access is also a DRAM page hit write access, said RAS# signal is active, and no refresh of said DRAM is pending; writing said data to said memory subsystem using a write-back policy if said cache hit write access is not also a DRAM page hit write access; writing said data to said memory subsystem using a write-back policy also if said RAS# signal is inactive; and writing said data to said memory subsystem using a write-back policy also if a refresh of said DRAM is pending.
Claim 12
Independent Claim
194 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; determining whether a refresh of said DRAM is pending; writing said data to said memory subsystem using a write-through policy only if said cache hit write access is also a DRAM page hit write access, said RAS# signal is active, and no refresh of said DRAM is pending; writing said data to said memory subsystem using a write-back policy if said cache hit write access is not also a DRAM page hit write access; writing said data to said memory subsystem using a write-back policy also if said RAS# signal is inactive; and writing said data to said memory subsystem using a write-back policy also if a refresh of said DRAM is pending.
Claim 13
Independent Claim
157 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; writing said data to said memory subsystem using a write-through policy if said cache hit write access is also a DRAM page hit write access; writing said data to said memory subsystem using a write-through policy also if said RAS# signal is inactive; and writing said data to said memory subsystem using a write-back policy only if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active.
Claim 14
Independent Claim
157 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; writing said data to said memory subsystem using a write-through policy if said cache hit write access is also a DRAM page hit write access; writing said data to said memory subsystem using a write-through policy also if said RAS# signal is inactive; and writing said data to said memory subsystem using a write-back policy only if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active.
Claim 15
Independent Claim
201 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; determining whether a refresh of said DRAM is pending; writing said data to said memory subsystem using a write-through policy if said cache hit write access is also a DRAM page hit write access and no refresh of said DRAM is pending; writing said data to said memory subsystem using a write-through policy also if said RAS# signal is inactive and no refresh of said DRAM is pending; writing said data to said memory subsystem using a write-back policy if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active; and writing said data to said memory subsystem using a write-back policy also if a refresh of said DRAM is pending.
Claim 16
Independent Claim
201 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; determining whether a refresh of said DRAM is pending; writing said data to said memory subsystem using a write-through policy if said cache hit write access is also a DRAM page hit write access and no refresh of said DRAM is pending; writing said data to said memory subsystem using a write-through policy also if said RAS# signal is inactive and no refresh of said DRAM is pending; writing said data to said memory subsystem using a write-back policy if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active; and writing said data to said memory subsystem using a write-back policy also if a refresh of said DRAM is pending.
Claim 17
Dependent Claim
119 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, for use in response to a cache hit data write access, comprising: first determining means for determining whether said cache hit write access is also a DRAM page hit write access; means, responsive to said first determining means, for writing said data to said memory subsystem using a write-through policy only if said cache hit write access is also a DRAM page hit write access; and means, responsive to said second determining means, for writing said data to said memory subsystem using a write-back policy if said cache hit write access is not also a DRAM page hit write access.
Claim 18
Dependent Claim
119 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, for use in response to a cache hit data write access, comprising: first determining means for determining whether said cache hit write access is also a DRAM page hit write access; means, responsive to said first determining means, for writing said data to said memory subsystem using a write-through policy only if said cache hit write access is also a DRAM page hit write access; and means, responsive to said second determining means, for writing said data to said memory subsystem using a write-back policy if said cache hit write access is not also a DRAM page hit write access.
Claim 19
Dependent Claim
184 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, for use in response to a cache hit data write access, comprising: first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; means, responsive to said first determining means, for writing said data to said memory subsystem using a write-through policy only if said cache hit write access is also a DRAM page hit write access and said RAS# signal is active; means, responsive to said second determining means, for writing said data to said memory subsystem using a write-back policy if said cache hit write access is not also a DRAM page hit write access; and means, responsive to said second determining means, for writing said data to said memory subsystem using a write-back policy also if said RAS# signal is inactive.
Claim 20
Dependent Claim
184 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, for use in response to a cache hit data write access, comprising: first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; means, responsive to said first determining means, for writing said data to said memory subsystem using a write-through policy only if said cache hit write access is also a DRAM page hit write access and said RAS# signal is active; means, responsive to said second determining means, for writing said data to said memory subsystem using a write-back policy if said cache hit write access is not also a DRAM page hit write access; and means, responsive to said second determining means, for writing said data to said memory subsystem using a write-back policy also if said RAS# signal is inactive.
Claim 21
Dependent Claim
235 words
Memory management apparatus for use with memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, for use in response to a cache hit data write access, comprising: first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; third determining means for determining whether a refresh of said DRAM is pending; means, responsive to said first, second and third determining means, for writing said data to said memory subsystem using a write-through policy only if said cache hit write access is also a DRAM page hit write access, said RAS# signal is active, and no refresh of said DRAM is pending; means, responsive to said first determining means, for writing said data to said memory subsystem using a write-back policy if said cache hit write access is not also a DRAM page hit write access; means, responsive to said second determining means, for writing said data to said memory subsystem using a write-back policy also if said RAS# signal is inactive; and means, responsive to said third determining means, for writing said data to said memory subsystem using a write-back policy also if a refresh of said DRAM is pending.
Claim 22
Dependent Claim
235 words
Memory management apparatus for use with memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, for use in response to a cache hit data write access, comprising: first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; third determining means for determining whether a refresh of said DRAM is pending; means, responsive to said first, second and third determining means, for writing said data to said memory subsystem using a write-through policy only if said cache hit write access is also a DRAM page hit write access, said RAS# signal is active, and no refresh of said DRAM is pending; means, responsive to said first determining means, for writing said data to said memory subsystem using a write-back policy if said cache hit write access is not also a DRAM page hit write access; means, responsive to said second determining means, for writing said data to said memory subsystem using a write-back policy also if said RAS# signal is inactive; and means, responsive to said third determining means, for writing said data to said memory subsystem using a write-back policy also if a refresh of said DRAM is pending.
Claim 23
Dependent Claim
174 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, comprising: first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; means, responsive to said first determining means, for writing said data to said memory subsystem using a write-through policy if said cache hit write access is also a DRAM page hit write access; means, responsive to said second determining means, for writing said data to said memory subsystem using a write-through policy also if said RAS# signal is inactive; and means, responsive to said first and second determining means, for writing said data to said memory subsystem using a write-back policy only if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active.
Claim 24
Dependent Claim
174 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, comprising: first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; means, responsive to said first determining means, for writing said data to said memory subsystem using a write-through policy if said cache hit write access is also a DRAM page hit write access; means, responsive to said second determining means, for writing said data to said memory subsystem using a write-through policy also if said RAS# signal is inactive; and means, responsive to said first and second determining means, for writing said data to said memory subsystem using a write-back policy only if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active.
Claim 25
Dependent Claim
234 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, comprising: first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; third determining means for determining whether a refresh of said DRAM is pending; means, responsive to said first and third determining means, for writing said data to said memory subsystem using a write-through policy if said cache hit write access is also a DRAM page hit write access and no refresh of said DRAM is pending; means, responsive to said second and third determining means, for writing said data to said memory subsystem using a write-through policy also if said RAS# signal is inactive and no refresh of said DRAM is pending; means, responsive to said first and second determining means, for writing said data to said memory subsystem using a write-back policy if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active; and means, responsive to said third determining means, for writing said data to said memory subsystem using a write-back policy also if a refresh of said DRAM is pending.
Claim 26
Dependent Claim
234 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, comprising: first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; third determining means for determining whether a refresh of said DRAM is pending; means, responsive to said first and third determining means, for writing said data to said memory subsystem using a write-through policy if said cache hit write access is also a DRAM page hit write access and no refresh of said DRAM is pending; means, responsive to said second and third determining means, for writing said data to said memory subsystem using a write-through policy also if said RAS# signal is inactive and no refresh of said DRAM is pending; means, responsive to said first and second determining means, for writing said data to said memory subsystem using a write-back policy if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active; and means, responsive to said third determining means, for writing said data to said memory subsystem using a write-back policy also if a refresh of said DRAM is pending.
References Cited (Backward Citations)
US4426682A
Cited
US4493026A
Cited
US4713755A
Cited
US4794523A
Cited
US4953073A
Cited
EP0231574A2
Cited
US5113506A
Cited
US4805098A
Cited
US5091846A
Cited
US4833599A
Cited
US4920477A
Cited
US5057837A
Cited
US4959777A
Cited
US5157774A
Cited
US5091850A
Cited
US4847758A
Cited
US5008813A
Cited
US5095428A
Cited
US5222224A
Cited
US5097532A
Cited
US5119485A
Cited
US5303364A
Cited
US5257360A
Cited
US5285323A
Cited
US5249283A
Cited
US5303362A
Cited
US5301298A
Cited
US5182802A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
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| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |