System for fast selection of non-cacheable address ranges using programmed array logic

Claim 1

A computer system capable of designating selected portions of memory as containing non-cacheable data, comprising: (a) a microprocessor which generates memory addresses and memory controls; (b) a main memory; (c) a cache controller receiving memory addresses and memory controls from said processor; (d) a cache memory coupled to said cache controller; and (e) an address decoder comprising programmed array logic programmed to satisfy the following logic equations: ##EQU1## where: A17-A31=input address lines from said microprocessor; CPROM=a second input software-selectable diagnostic bit from said microprocessor for designating whether a high-memory copy of said system ROM is being utilized; 512K and 640K=input lines from said microprocessor for indicating the desired size of the base memory; NA=an output signal the inverse of which is sent to a designated port of said microprocessor requesting the next address; and NCA=an output signal the inverse of which is sent to a designated port of said cache controller indicating whether said address from said microprocessor contains non-cacheable data; *=a Boolean AND operation; +=a Boolean OR operation; and /=a NOT or inversion operation.