Cache flush request circuit flushes the cache if input/output space write operation and circuit board response are occurring concurrently

Claim 1

A cache flush request circuit for use in a computer system having a memory address space and an input/output address space, the computer system including cache memory which stores data held in the memory address space, a cache memory controller coupled to the cache memory having a cache flush request input, a system signal bus having address, data and control signals, a plurality of circuit board receiving locations connected to the system signal bus for insertion of circuit boards, which circuit boards are addressed over the system signal bus and which have a register that has data provided by signals presented on the system signal bus representing an input/output space operation or which are initialized by signals presented on the system signal bus, the cache flush request circuit comprising: means connected to said system signal bus for determining when an input/output space write operation is occurring; means connected to said system signal bus for determining if an installed circuit board is responding to an operation requested over said system signal bus; and means responsive to said input/output space write operation determining means and to said installed circuit board responding determining means for determining if said input/output space write operation and said circuit board response are occurring concurrently and producing a cache flush request signal which is connected to the cache flush request input of the cache memory controller if said input/output space write operation and said circuit board response are occurring concurrently.