Loc simm

Claim 2

A multi-chip module, comprising: a carrier substrate having a top side and a bottom side, said carrier substrate defining a plurality of openings extending between said top side and said bottom side and a plurality of recesses partially extending into said bottom side, each aligned with one of said plurality of openings; and a plurality of semiconductor dice, each having an active surface including a plurality of bond pads thereon, at least a portion of at least one of said plurality of semiconductor dice secured at least partially within one of said plurality of recesses with said active surface facing said carrier substrate and said plurality of bond pads exposed through said one of said plurality of openings.

Claim 3

The multi-chip module of claim 1, wherein said substrate carrier includes a plurality of conductive traces on said top side proximate each of said plurality of openings that extends over at least a portion of each of said plurality of semiconductor dice.

Claim 4

The multi-chip module of claim 2, further including a plurality of wire bonds between at least some of said plurality of bond pads and at least some of said plurality of conductive traces.

Claim 5

The multi-chip module of claim 3, further including an adhesive bond between each of said plurality of semiconductor dice and said carrier substrate.

Claim 6

The multi-chip module of claim 4, wherein said adhesive bond removably attaches each of said plurality of semiconductor dice to said carrier substrate.

Claim 7

The multi-chip module of claim 4, further including a non-conductive glob top over said plurality of wire bonds and a substantial portion of each of said plurality of semiconductor dice.

Claim 8

The multi-chip module of claim 1, further including a wall around a perimeter of said bottom side.

Claim 9

The multi-chip module of claim 7, further including a lid attached to said carrier substrate wall.

Claim 10

The multi-chip module of claim 1, further including a wall around a perimeter of said top side.

Claim 11

The multi-chip module of claim 9, further including a lid attached to said carrier substrate wall.

Claim 12

The multi-chip module of claim 2, wherein at least some of said plurality of bond pads are connected to at least some of said plurality of conductive traces using a TAB attach.

Claim 13

The multi-chip module of claim 4, wherein at least one of said plurality of semiconductor dice is received completely within one of said plurality of recesses, and further including a lid over said carrier substrate bottom surface over said completely received die.

Claim 14

The multi-chip module of claim 3, wherein at least one of said plurality of semiconductor dice is a defective die, the plurality of wire bonds of said at least one defective die is disconnected from said plurality of conductive traces, and further including at least one known good die attached to said top side in replacement of said defective die and in electrical communication with at least some of said conductive traces.

Claim 15

The multi-chip module of claim 13, wherein said at least one replacement die is a known good die.

Claim 16

The multi-chip module of claim 13, wherein said at least one known good die is attached to said carrier substrate over the opening associated with said defective die.

Claim 17

The multi-chip module of claim 15, wherein said at least one known good die is back-attached to said top side and electrically connected to at least some of said conductive traces by intermediate conductive elements.

Claim 18

The multi-chip module of claim 16, wherein at least some of said conductive traces proximate said carrier substrate opening over which said known good die is attached extend away from that opening for a distance sufficient to clear a perimeter of said plurality of known good die as attached and permit attachment of said intermediate conductive elements thereto.

Claim 19

The multi-chip module of claim 15, wherein said at least one known good die is attached with an active surface facing said carrier substrate top side, and electrically connected to at least some of said plurality of conductive traces by conductive protrusions extending transversely from said active surface to said plurality of conductive traces.

Claim 20

A memory module, comprising: a carrier substrate having a top side and a bottom side, said carrier substrate defining a plurality of openings therethrough; a plurality of semiconductor dice, including at least one defective die, each having an active surface including a plurality of bond pads thereon, at least a portion of said active surface of each of said plurality of semiconductor dice attached to said bottom side of said carrier substrate with a plurality of said bond pads of each of said plurality of semiconductor dice exposed through one of said plurality of openings; a plurality of conductive traces on said carrier substrate top side proximate each of said plurality of openings extending over at least a portion of each of said plurality of semiconductor dice; a plurality of wire bonds between at least some of said exposed plurality of bond pads and at least some of said plurality of conductive traces; and at least one known good die attached to said carrier substrate top side in replacement of said at least one defective die and in electrical communication with at least some of said conductive traces.

Claim 21

A memory module, comprising: a carrier substrate having a top side and a bottom side, said carrier substrate defining a plurality of openings therethrough; a plurality of semiconductor dice, including at least one defective die, each having an active surface including a plurality of bond pads thereon, at least a portion of said active surface of each of said plurality of semiconductor dice attached to said bottom side of said carrier substrate with a plurality of said bond pads of each of said plurality of semiconductor dice exposed through one of said plurality of openings; a plurality of conductive traces on said carrier substrate top side proximate each of said plurality of openings extending over at least a portion of each of said plurality of semiconductor dice; a plurality of wire bonds between at least some of said exposed plurality of bond pads and at least some of said plurality of conductive traces; and at least one known good die attached to said carrier substrate top side in replacement of said at least one defective die and in electrical communication with at least some of said conductive traces.

Claim 22

The module of claim 19, wherein said at least one known good die is attached to said carrier substrate over the opening associated with said at least one defective die.

Claim 23

The module of claim 20, wherein said at least one known good die is back-attached to said carrier substrate top side and electrically connected to at least some of said conductive traces by intermediate conductive elements.

Claim 24

The module of claim 21, wherein at least some of said conductive traces proximate said opening over which said at least one known good die is attached extend away from that opening for a distance sufficient to clear a perimeter of said at least one known good die as attached and permit attachment of said intermediate conductive elements thereto.

Claim 25

The module of claim 19, wherein said at least one known good die is attached with its active surface facing said carrier substrate top side, and electrically connected to at least some of said conductive traces by conductive protrusions extending transversely from said active surface to said traces.