US5723358A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing amorphous silicon antifuse structures

Assignee: Philips Semiconductors Inc

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Filing: 1996-04-29

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Granted: 1998-03-03

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Expires: 2016-04-29

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Abstract

Abstract Disclosed is an apparatus and method for manufacturing antifuse structures on topographically varying silicon substrates. The antifuse structures are intelligently formed over topographically lower silicon substrate regions such that subsequent via hole etching processes do not over-etch underlying antifuse structures. Also discloses an apparatus and method for designing dummy metallization and polysilicon features in close proximity to antifuse structures such that subsequently deposited dielectric materials are induced to form thicker dielectric layers over antifuse structures. Advantageously, subsequent via hole etching does not substantially remove antifuse structure materials with may cause detrimental ionic contamination or antifuse infant mortality. In this manner, standard via hole etching techniques may be implemented for all inter-layer via holes without concern the concern of over-etching sensitive underlying devices.

Inventors

👤 Martin Harold Manley

Bibliographic Details

Application Number —

Jurisdiction US

Data Source google_patents

Last Synchronized 2026-11-06 08:39

CPC Classifications

H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/065; H10W20/40; H10W20/49; H10W20/491; Y; Y10; Y10S; Y10S148/00; Y10S148/055

Claims Analysis

Total Claims: 11

Claim 1

Independent Claim 212 words

A method of fabricating an integrated circuit device, the method comprising the steps of: providing a substrate having a plurality of active regions, a plurality of dummy diffusion regions and a plurality of field oxide regions that are raised relative to the active and dummy diffusion regions; depositing a first dielectric layer over the substrate such that the first dielectric layer produces topographically lower regions over the plurality of active regions and dummy diffusion regions and topographically higher regions over the field oxide regions; depositing a first metallization layer defining a network of metallization lines, at least some of the metallization lines being arranged to electrically interconnect preselected ones of the plurality of active regions, wherein at least some of the metallization lines pass over associated field oxide regions; forming an antifuse over the first dielectric layer such that the antifuse is positioned over a topographically lower dummy diffusion region, and depositing a second dielectric layer over the first dielectric layer and the first metallization layer, and etching a multiplicity of via holes through the second dielectric layer such that at least some of the via holes are formed to communicate with segments of the metallization layer and at least one of the via holes is positioned to communicate with the antifuse.

Claim 2

Independent Claim 212 words

Claim 3

Dependent Claim 41 words

The method of fabricating an integrated circuit device of claim 1, wherein the step of etching the multiplicity of via holes does not require etching via holes that are significantly deeper than the via hole designed to communicate with the antifuse.

Claim 4

Dependent Claim 98 words

The method of fabricating an integrated circuit device of claim 1, wherein the step of forming the antifuse further includes the substeps of: forming an intermediate dielectric layer over the first metallization layer such that a via-link opening is provided in the intermediate dielectric layer to provide an electrical path with the first metallization layer; forming an amorphous silicon layer over the intermediate dielectric layer such that the amorphous silicon layer makes direct contact with the first metallization layer through the via link opening in the intermediate dielectric; and forming a barrier layer over the amorphous silicon layer.

Claim 5

Dependent Claim 38 words

The method of fabricating an integrated circuit device of claim 3, wherein the step of forming the barrier layer includes depositing the barrier layer to a thickness in the range of approximately 500 Å to approximately 2,000 Å.

Claim 6

Dependent Claim 57 words

The method of fabricating an integrated circuit device of claim 1, further including the substep of: forming a plurality of dummy polysilicon segments between the substrate and the first dielectric layer such that selected ones of the plurality of dummy polysilicon segments form a topographically raised region for the first dielectric layer and the first metallization layer.

Claim 7

Dependent Claim 64 words

The method of fabricating an integrated circuit device of claim 5, wherein the step of forming the dummy polysilicon segments further includes the substep of: forming the polysilicon segments over selected ones of the plurality of field oxide regions such that the first metallization lines are generally vertically aligned over selected ones of the plurality of field oxide regions and the dummy polysilicon segments.

Claim 8

Dependent Claim 37 words

The method of fabricating an integrated circuit device of claim 1, wherein the step of forming the first dielectric layer includes depositing first dielectric layer to a thickness of between approximately 6,000 Å and approximately 12,000 Å.

Claim 9

Dependent Claim 36 words

The method of fabricating an integrated circuit device of claim 1, wherein the step of forming the second dielectric layer includes depositing the dielectric layer to a thickness between approximately 6,000 Å and approximately 15,000 Å.

Claim 10

Dependent Claim 31 words

The integrated circuit device as recited in claim 1, further including the step of growing at least some of the plurality of field oxide regions to approximately 5000 Å in thickness.

Claim 11

Dependent Claim 37 words

The integrated circuit device as recited in claim 5, further including the step of depositing at least some of the plurality of dummy polysilicon segments to a thickness ranging between approximately 2,500 Å to approximately 5000 Å.

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USPTO Annuity & Maintenance Windows

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-03-02	2001-09-01	2002-03-03	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-03-02	2005-09-01	2006-03-03	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-03-02	2009-09-01	2010-03-03	$7700.00	Window Closed / Lapsed

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