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US5714788A Expired / Lapsed US ⏱️ 0.0 years remaining

Dual ion implantation process for gate oxide improvement

Assignee: GlobalFoundries Singapore Pte Ltd
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Filing: 1996-12-16
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Granted: 1998-02-03
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Expires: 2016-12-16
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Abstract

Abstract A method for improving oxide quality by implanting both nitrogen and fluorine ions into the oxide layer through a polysilicon layer to prevent the penetration of impurities into the oxide layer is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. Fluorine ions are implanted through the polysilicon layer wherein the fluorine ions congregate at the interface between the gate silicon oxide layer and the surface of the semiconductor substrate. Thereafter, nitrogen ions are implanted through the polysilicon layer wherein the nitrogen ions congregate at the interface between the gate silicon oxide layer and the surface of the semiconductor substrate. The substrate is annealed. The polysilicon and gate silicon oxide layers are patterned to form gate electrodes and interconnection lines. Source/drain ions are implanted to form source and drain regions within the semiconductor substrate using the gate electrodes and interconnection lines as a mask. Metallization with electrical connections completes the fabrication of the integrated circuit device.

Inventors

  • 👤 Sukhum Ngaoaram

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 04:37
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01338; H10D64/693

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 91 words
An integrated circuit device comprising: a patterned layer of gate silicon oxide over the surface of a semiconductor substrate; a concentration of oxy-fluoro-nitride at the interface between said gate silicon oxide layer and said semiconductor substrate; a patterned polysilicon layer overlying said patterned gate silicon oxide layer; source and drain regions within said semiconductor substrate; an insulating layer overlying said patterned polysilicon and gate silicon oxide layers; a metal layer contacting said source and drain regions through openings in said insulating layer to complete electrical connections in said integrated circuit device.
Claim 2
Dependent Claim 91 words
An integrated circuit device comprising: a patterned layer of gate silicon oxide over the surface of a semiconductor substrate; a concentration of oxy-fluoro-nitride at the interface between said gate silicon oxide layer and said semiconductor substrate; a patterned polysilicon layer overlying said patterned gate silicon oxide layer; source and drain regions within said semiconductor substrate; an insulating layer overlying said patterned polysilicon and gate silicon oxide layers; a metal layer contacting said source and drain regions through openings in said insulating layer to complete electrical connections in said integrated circuit device.
Claim 3
Dependent Claim 22 words
The device according to claim 1 wherein said gate silicon oxide layer has a thickness of between about 80 to 150 Angstroms.
Claim 4
Dependent Claim 17 words
The device according to claim 1 wherein said oxy-fluoro-nitride concentration has a thickness of about 20 Angstroms.
Claim 5
Dependent Claim 20 words
The device according to claim 1 wherein said polysilicon layer has a thickness of between about 1500 to 2000 Angstroms.
Claim 6
Dependent Claim 40 words
The device according to claim 1 wherein said oxy-fluoro-nitride concentration at said interface between said gate silicon oxide and said semiconductor substrate surface prevents the penetration of ions from said source and drain regions into said gate silicon oxide layer.

References Cited (Backward Citations)

US4897368A Cited
US5108935A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-02-02 2001-08-04 2002-02-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-02-02 2005-08-04 2006-02-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-02-02 2009-08-04 2010-02-03 $7700.00 Window Closed / Lapsed

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