US5480828A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1994-09-30
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Granted: 1996-01-02
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Expires: 2014-09-30
Abstract
Abstract A new method of simultaneously forming differential gate oxide for both 3 and 5 V transistors is described. A sacrificial silicon oxide layer is formed on the surface of a semiconductor substrate. Ions are implanted through the sacrificial silicon oxide layer into the planned 3 V transistor area of the semiconductor substrate wherein the implanted ions depress the oxidation rate of the semiconductor substrate. Alternatively, ions are implanted through the sacrificial silicon oxide layer into the planned 5 V transistor area of the semiconductor substrate wherein the implanted ions increase the oxidation rate of the semiconductor substrate. The sacrificial silicon oxide layer is removed and a layer of gate silicon oxide is grown on the surface of the semiconductor substrate. The growth rate of the gate silicon oxide will be slowed in the planned 3 V transistor area or will be increased in the planned 5 V transistor area resulting in a gate silicon oxide layer which is relatively thinner in the planned 3 V transistor area and relatively thicker in the planned 5 V transistor area. A layer of polysilicon is deposited over the gate silicon oxide layer and patterned to form gate electrodes for the 3V and 5V transistors.
Inventors
- 👤 Shun-Liang Hsu
- 👤 Jyh-Min Tsaur
- 👤 Mou S. Lin
- 👤 Jyh-Kang Ting
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:31
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/116; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
258 words
The method of simultaneously forming both a 3 and a 5 V transistor in the manufacture of an integrated circuit comprising: forming a sacrificial silicon oxide layer on the surface of a semiconductor substrate; implanting ions through said sacrificial silicon oxide layer into an area of said semiconductor substrate where said 3 V transistor is to be formed wherein said ions depress the oxidation rate of said semiconductor substrate and wherein annealing is not required; removing said sacrificial silicon oxide layer; growing a layer of gate silicon oxide on the surface of said semiconductor substrate wherein the growth rate of said gate silicon oxide will be slower in said 3 V transistor area and wherein said gate silicon oxide layer will be thinner in said 3 V transistor area than the gate oxide layer in said 5 V transistor area; depositing a layer of polysilicon over said gate silicon oxide layer and patterning said polysilicon layer to form gate electrodes for said 3 V and said 5 V transistors; forming source and drain regions within said semiconductor substrate adjoining said 3 V and said 5 V transistors; depositing a dielectric layer overlying the top surface of said semiconductor substrate and said 3 V and said 5 V transistors; forming openings within said dielectric layer to said underlying source and drain regions where electrical connections are to be made to said 3 V and said 5 V transistors; and filling said openings with a patterned metal layer to complete said electrical connections in the fabrication of said integrated circuit.
Claim 2
Independent Claim
258 words
The method of simultaneously forming both a 3 and a 5 V transistor in the manufacture of an integrated circuit comprising: forming a sacrificial silicon oxide layer on the surface of a semiconductor substrate; implanting ions through said sacrificial silicon oxide layer into an area of said semiconductor substrate where said 3 V transistor is to be formed wherein said ions depress the oxidation rate of said semiconductor substrate and wherein annealing is not required; removing said sacrificial silicon oxide layer; growing a layer of gate silicon oxide on the surface of said semiconductor substrate wherein the growth rate of said gate silicon oxide will be slower in said 3 V transistor area and wherein said gate silicon oxide layer will be thinner in said 3 V transistor area than the gate oxide layer in said 5 V transistor area; depositing a layer of polysilicon over said gate silicon oxide layer and patterning said polysilicon layer to form gate electrodes for said 3 V and said 5 V transistors; forming source and drain regions within said semiconductor substrate adjoining said 3 V and said 5 V transistors; depositing a dielectric layer overlying the top surface of said semiconductor substrate and said 3 V and said 5 V transistors; forming openings within said dielectric layer to said underlying source and drain regions where electrical connections are to be made to said 3 V and said 5 V transistors; and filling said openings with a patterned metal layer to complete said electrical connections in the fabrication of said integrated circuit.
Claim 3
Dependent Claim
19 words
The method of claim 1 wherein said sacrificial oxide has a thickness of between about 200 to 400 Angstroms.
Claim 4
Dependent Claim
40 words
The method of claim 1 wherein said ions are nitrogen ions implanted into said semiconductor substrate with a dose of between about 1 E 14 to 3 E 14 atoms/cm 2 and energy of between about 30 to 50 KeV.
Claim 5
Dependent Claim
47 words
The method of claim 1 wherein said gate silicon oxide layer in said 3 V transistor area has a thickness of between about 70 to 100 Angstroms and wherein said gate silicon oxide layer in said 5 V transistor area has a thickness of about 140 Angstroms.
Claim 6
Independent Claim
255 words
The method of simultaneously forming both a 3 and a 5 V transistor in the manufacture of an integrated circuit comprising: forming a sacrificial silicon oxide layer on the surface of a semiconductor substrate; implanting fluorine ions through said sacrificial silicon oxide layer into an area of said semiconductor substrate where said 5 V transistor is to be formed wherein said fluorine ions increase the oxidation rate of said semiconductor substrate; removing said sacrificial silicon oxide layer; growing a layer of gate silicon oxide on the surface of said semiconductor substrate wherein the growth rate of said gate silicon oxide will be faster in said 5 V transistor area and wherein said gate silicon oxide layer will be thicker in said 5 V transistor area than the gate silicon oxide layer in the 3 V transistor area; depositing a layer of polysilicon over said gate silicon oxide layer and patterning said polysilicon layer to form gate electrodes for said 3 V and said 5 V transistors; forming source and drain regions within said semiconductor substrate adjoining said 3 V and said 5 V transistors; depositing a dielectric layer overlying the top surface of said semiconductor substrate and said 3 V and said 5 V transistorst; forming openings within said dielectric layer to said underlying source and drain regions where electrical connections are to be made to said 3 V and said 5 V transistors; and filling said openings with a patterned metal layer to complete said electrical connections in the fabrication of said integrated circuit.
Claim 7
Independent Claim
255 words
The method of simultaneously forming both a 3 and a 5 V transistor in the manufacture of an integrated circuit comprising: forming a sacrificial silicon oxide layer on the surface of a semiconductor substrate; implanting fluorine ions through said sacrificial silicon oxide layer into an area of said semiconductor substrate where said 5 V transistor is to be formed wherein said fluorine ions increase the oxidation rate of said semiconductor substrate; removing said sacrificial silicon oxide layer; growing a layer of gate silicon oxide on the surface of said semiconductor substrate wherein the growth rate of said gate silicon oxide will be faster in said 5 V transistor area and wherein said gate silicon oxide layer will be thicker in said 5 V transistor area than the gate silicon oxide layer in the 3 V transistor area; depositing a layer of polysilicon over said gate silicon oxide layer and patterning said polysilicon layer to form gate electrodes for said 3 V and said 5 V transistors; forming source and drain regions within said semiconductor substrate adjoining said 3 V and said 5 V transistors; depositing a dielectric layer overlying the top surface of said semiconductor substrate and said 3 V and said 5 V transistorst; forming openings within said dielectric layer to said underlying source and drain regions where electrical connections are to be made to said 3 V and said 5 V transistors; and filling said openings with a patterned metal layer to complete said electrical connections in the fabrication of said integrated circuit.
Claim 8
Dependent Claim
19 words
The method of claim 5 wherein said sacrificial oxide has a thickness of between about 200 to 400 Angstroms.
Claim 9
Dependent Claim
39 words
The method of claim 5 wherein said fluorine ions are implanted into said semiconductor substrate with a dose of between about 7.5 E 15 to 3 E 16 atoms/cm 2 and energy of between about 25 to 45 KeV.
Claim 10
Dependent Claim
47 words
The method of claim 5 wherein said gate silicon oxide layer in said 5 V transistor area has a thickness of between about 110 to 120 Angstroms and wherein said gate silicon oxide layer in said 3 V transistor area has a thickness of about 100 Angstroms.
Claim 11
Independent Claim
230 words
The method of simultaneously forming both a 3 V and a 5 V transistor in the manufacture of an integrated circuit comprising: forming a gate silicon oxide layer on the surface of a semiconductor substrate; depositing a polysilicon layer overlying the gate silicon oxide layer; implanting ions into said polysilicon layer in the 5 V transistor area of said semiconductor substrate; annealing said substrate wherein said ions displace oxygen within said gate silicon oxide layer and wherein said displaced oxygen oxidizes said polysilicon layer resulting in an increased thickness gate silicon oxide layer in said 5 V transistor area wherein said gate silicon oxide layer will be thicker in said 5 V transistor area than the gate silicon oxide in said 3 V transistor area; patterning said polysilicon layer to form gate electrodes for said 3 V and said 5 V transistors; forming source and drain regions within said semiconductor substrate adjoining said 3 V and said 5 V transistors; depositing a dielectric layer overlying the top surface of said semiconductor substrate and said 3 V said 5 V transistors; forming openings within said dielectric layer to said underlying source and drain regions where electrical connections are to be made to said 3 V and said 5 V transistors; and filling said openings with a patterned metal layer to complete said electrical connections in the fabrication of said integrated circuit.
Claim 12
Independent Claim
230 words
The method of simultaneously forming both a 3 V and a 5 V transistor in the manufacture of an integrated circuit comprising: forming a gate silicon oxide layer on the surface of a semiconductor substrate; depositing a polysilicon layer overlying the gate silicon oxide layer; implanting ions into said polysilicon layer in the 5 V transistor area of said semiconductor substrate; annealing said substrate wherein said ions displace oxygen within said gate silicon oxide layer and wherein said displaced oxygen oxidizes said polysilicon layer resulting in an increased thickness gate silicon oxide layer in said 5 V transistor area wherein said gate silicon oxide layer will be thicker in said 5 V transistor area than the gate silicon oxide in said 3 V transistor area; patterning said polysilicon layer to form gate electrodes for said 3 V and said 5 V transistors; forming source and drain regions within said semiconductor substrate adjoining said 3 V and said 5 V transistors; depositing a dielectric layer overlying the top surface of said semiconductor substrate and said 3 V said 5 V transistors; forming openings within said dielectric layer to said underlying source and drain regions where electrical connections are to be made to said 3 V and said 5 V transistors; and filling said openings with a patterned metal layer to complete said electrical connections in the fabrication of said integrated circuit.
Claim 13
Dependent Claim
18 words
The method of claim 9 wherein said gate silicon oxide layer has a thickness of about 100 Angstroms.
Claim 14
Dependent Claim
40 words
The method of claim 9 wherein said ions are fluorine ions implanted into said polysilicon layer with a dose of between about 7.5 E 15 to 3 E 16 atoms/cm 2 and energy of between about 70 to 110 KeV.
Claim 15
Dependent Claim
30 words
The method of claim 9 wherein said substrate is annealed at a temperature of between about 900° to 950° C. for a duration of between about 30 to 60 minutes.
Claim 16
Dependent Claim
47 words
The method of claim 9 wherein said gate silicon oxide layer in said 5 V transistor area has a thickness of between about 110 to 120 Angstroms and wherein said gate silicon oxide layer in said 3 V transistor area has a thickness of about 100 Angstroms.
Claim 17
Independent Claim
246 words
The method of simultaneously forming both a 3 V and a 5 V transistor in the manufacture of an integrated circuit comprising: forming a gate silicon oxide layer having a thickness of about 100 Angstroms on the surface of a semiconductor substrate; depositing a polysilicon layer overlying the gate silicon oxide layer; implanting ions into said polysilicon layer in the 5 V transistor area of said semiconductor substrate; annealing said substrate wherein said ions displace oxygen within said gate silicon oxide layer and wherein said displaced oxygen oxidizes said polysilicon layer resulting in an increased thickness gate silicon oxide layer in said 5 V transistor area wherein said gate silicon oxide layer will be between about 110 to 120 Angstroms thick in said 5 V transistor area and will be about 100 Angstroms thick in said 3 V transistor area; patterning said polysilicon layer to form gate electrodes for said 3 V and said 5 V transistors; forming source and drain regions within said semiconductor substrate adjoining said 3 V and said 5 V transistors; depositing a dielectric layer overlying the top surface of said semiconductor substrate and said 3 V and said 5 V transistors; forming openings within said dielectric layer to said underlying source and drain regions where electrical connections are to be made to said 3 V and said 5 V transistors; and filling said openings with a patterned metal layer to complete said electrical connections in the fabrication of said integrated circuit.
Claim 18
Independent Claim
246 words
The method of simultaneously forming both a 3 V and a 5 V transistor in the manufacture of an integrated circuit comprising: forming a gate silicon oxide layer having a thickness of about 100 Angstroms on the surface of a semiconductor substrate; depositing a polysilicon layer overlying the gate silicon oxide layer; implanting ions into said polysilicon layer in the 5 V transistor area of said semiconductor substrate; annealing said substrate wherein said ions displace oxygen within said gate silicon oxide layer and wherein said displaced oxygen oxidizes said polysilicon layer resulting in an increased thickness gate silicon oxide layer in said 5 V transistor area wherein said gate silicon oxide layer will be between about 110 to 120 Angstroms thick in said 5 V transistor area and will be about 100 Angstroms thick in said 3 V transistor area; patterning said polysilicon layer to form gate electrodes for said 3 V and said 5 V transistors; forming source and drain regions within said semiconductor substrate adjoining said 3 V and said 5 V transistors; depositing a dielectric layer overlying the top surface of said semiconductor substrate and said 3 V and said 5 V transistors; forming openings within said dielectric layer to said underlying source and drain regions where electrical connections are to be made to said 3 V and said 5 V transistors; and filling said openings with a patterned metal layer to complete said electrical connections in the fabrication of said integrated circuit.
Claim 19
Dependent Claim
40 words
The method of claim 14 wherein said ions are fluorine ions implanted into said polysilicon layer with a dose of between about 7.5 E 15 to 3 R 16 atoms/cm 2 and energy of between about 70 to 110 KeV.
Claim 20
Dependent Claim
30 words
The method of claim 14 wherein said substrate is annealed at a temperature of between about 900° to 950° C. for a duration of between about 30 to 60 minutes.
References Cited (Backward Citations)
US4651406A
Cited
US4716126A
Cited
US4748134A
Cited
US4948742A
Cited
JPH0433375A
Cited
JPH05275640A
Cited
US5330920A
Cited
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