Negative voltage switching circuit

Claim 2

A voltage switching circuit, comprising: (A) a low power switching circuit for selectively coupling a first voltage having a voltage level substantially lower than zero volts to an output of the low power switching circuit; and (B) a control circuit coupled to the low power switching circuit for controlling the low power switching circuit to couple the first voltage to the output by generating a second voltage having a voltage level lower than that of the first voltage from a third voltage having a voltage level substantially higher than zero volts, the control circuit including first and second capacitors alternatingly coupled to the low power switching circuit to generate the second voltage.

Claim 3

The voltage switching circuit of claim 1, wherein the low power switching circuit further comprises a P-channel switching transistor coupled between the output of the low power switching circuit and the first voltage.

Claim 4

The voltage switching circuit of claim 1, wherein the control circuit further comprises (a) the first capacitor having a first end and a second end; (b) the second capacitor having a first end and a second end; (c) a first logic circuit coupled to receive a periodic signal and coupled to the first end of each of the first and second capacitors for alternately coupling the first end of each of the first and second capacitors to one of (1) the third voltage and (2) ground under control of the periodic signal; and (d) a second logic circuit coupled to (1) the second end of each of the first and second capacitors and (2) the low power switching circuit for alternately coupling the second end of each of the first and second capacitors to the low power switching circuit, wherein when the second logic circuit couples the second end of the first capacitor to the low power switching circuit and the second end of the second capacitor to a fourth voltage, the first logic circuit couples the first end of the first capacitor to ground and the first end of the second capacitor to the third voltage.

Claim 5

The voltage switching circuit of claim 3, wherein the second logic circuit further comprises a plurality of cross-coupled P-channel transistors coupled between the first and second capacitors and the fourth voltage.

Claim 6

The voltage switching circuit of claim 3, wherein the first logic circuit further comprises a voltage translation circuit coupled to the third voltage, the periodic signal and ground.

Claim 7

A voltage switching circuit, comprising: (A) a low power switching circuit having a switching transistor coupled between a first voltage and an output, wherein the first voltage has a voltage level substantially lower than zero volts; (B) a first capacitor having a first end and a second end; (C) a second capacitor having a first end and a second end; (D) a first logic circuit coupled to the first end of each of the first and second capacitors for alternately coupling the first end of each of the first and second capacitors to one of (1) a second voltage having a voltage level higher than zero volts and (2) ground; and (E) a second logic circuit coupled to the second end of each of the capacitors and the gate of the switching transistor for alternately coupling the second end of each of the capacitors to the gate of the switching transistor such that a third voltage having a voltage level lower than that of the first voltage is generated and applied to the gate of the switching transistor for causing the switching transistor to couple the first voltage to the output.

Claim 8

A voltage switching circuit, comprising: (A) a low power switching circuit having a switching transistor coupled between a first voltage and an output, wherein the first voltage has a voltage level substantially lower than zero volts; (B) a first capacitor having a first end and a second end; (C) a second capacitor having a first end and a second end; (D) a first logic circuit coupled to the first end of each of the first and second capacitors for alternately coupling the first end of each of the first and second capacitors to one of (1) a second voltage having a voltage level higher than zero volts and (2) ground; and (E) a second logic circuit coupled to the second end of each of the capacitors and the gate of the switching transistor for alternately coupling the second end of each of the capacitors to the gate of the switching transistor such that a third voltage having a voltage level lower than that of the first voltage is generated and applied to the gate of the switching transistor for causing the switching transistor to couple the first voltage to the output.

Claim 9

The voltage switching circuit of claim 6, wherein when the second logic circuit couples the second end of the first capacitor to the gate of the switching transistor and the second end of the second capacitor to a fourth voltage, the first logic circuit couples the first end of the first capacitor to ground and the first end of the second capacitor to the second voltage.

Claim 10

The voltage switching circuit of claim 6, wherein the second logic circuit further comprises a plurality of cross-coupled P-channel transistors.

Claim 11

The voltage switching circuit of claim 7, wherein the first logic circuit further comprises (a) a gate circuit coupled to receive a periodic signal; (b) a voltage translation circuit coupled to the gate circuit for alternately coupling the first end of each of the capacitors to the second voltage under control of the gate circuit; and (c) a first inverter coupled between the voltage translation circuit and the first end of the first capacitor and a second inverter coupled between the voltage translation circuit and the first end of the second capacitor.

Claim 12

The voltage switching circuit of claim 7, further comprising (i) a de-coupling circuit coupled to the gate of the switching transistor for de-coupling the gate of the switching transistor from a fifth voltage having a voltage level higher than zero volts before the second voltage is applied to the gate of the switching transistor; and (ii) a clamping circuit coupled to the gate of the switching transistor for clamping the gate of the switching transistor above the fourth voltage having a voltage level lower than the third voltage when the second logic circuit alternately couples the second end of each of the capacitors to the gate of the switching transistor.

Claim 13

The voltage switching circuit of claim 10, wherein the decoupling circuit further comprises a P-channel transistor, wherein the clamping circuit further comprises a pair of P-channel transistors.

Claim 14

A nonvolatile memory, comprising: (A) a memory cell; (B) a low power word line driver coupled to a gate of the memory cell for selectively coupling a first voltage having a voltage level substantially lower than zero volts to the gate of the memory cell during a memory operation of the memory cell; and (C) a control circuit coupled to the word line driver for controlling the word line driver to couple the first voltage to the gate of the memory cell by generating a second voltage having a voltage level lower than that of the first voltage to control the word line driver to couple the first voltage to the gate of the memory cell, wherein the control circuit generate the second voltage from a third voltage having a voltage level substantially higher than zero volts, the control circuit including first and second capacitors alternatingly coupled to the word line driver to generate the second voltage.

Claim 15

A nonvolatile memory, comprising: (A) a memory cell; (B) a low power word line driver coupled to a gate of the memory cell for selectively coupling a first voltage having a voltage level substantially lower than zero volts to the gate of the memory cell during a memory operation of the memory cell; and (C) a control circuit coupled to the word line driver for controlling the word line driver to couple the first voltage to the gate of the memory cell by generating a second voltage having a voltage level lower than that of the first voltage to control the word line driver to couple the first voltage to the gate of the memory cell, wherein the control circuit generate the second voltage from a third voltage having a voltage level substantially higher than zero volts, the control circuit including first and second capacitors alternatingly coupled to the word line driver to generate the second voltage.

Claim 16

The nonvolatile memory of claim 12, wherein the word line driver further comprises (i) a first P-channel transistor coupled between a power supply and an output node, wherein the word line driver is coupled to the gate of the memory cell via the output node; (ii) a second P-channel transistor having a first end coupled to the output node; (iii) a first N-channel transistor coupled between a second end of the second P-channel transistor and ground; and (iv) a third P-channel transistor coupled between the output node and the first voltage, wherein when the third P-channel transistor couples the first voltage to the output node, the first and second P-channel transistors are turned off to isolate the output node from the power supply and ground.

Claim 17

The nonvolatile memory of claim 12, wherein the control circuit further comprises (a) the first capacitor having a first end and a second end; (b) the second capacitor having a first end and a second end; (c) a first logic circuit coupled to receive a periodic signal and to the first end of each of the first and second capacitors for alternately coupling the first end of each of the first and second capacitors to one of (1) the third voltage and (2) ground under control of the periodic signal; and (d) a second logic circuit coupled to (1) the second end of each of the first and second capacitors and (2) the word line driver for alternately coupling the second end of each of the first and second capacitors to the word line driver, wherein when the second logic circuit couples the second end of the first capacitor to the word line driver and the second end of the second capacitor to a fourth voltage, the first logic circuit couples the first end of the first capacitor to ground and the first end of the second capacitor to the third voltage.

Claim 18

The nonvolatile memory of claim 14, wherein the second logic circuit further comprises a plurality of cross-coupled P-channel transistors coupled between the first and second capacitors and the fourth voltage.

Claim 19

The nonvolatile memory of claim 14, wherein the first logic circuit further comprises a voltage translation circuit coupled to the third voltage, the periodic signal and ground.

Claim 20

The nonvolatile memory of claim 12, wherein the nonvolatile memory is an electrically erasable and programmable memory.

Claim 21

The nonvolatile memory of claim 12, wherein the nonvolatile memory is used in a computer system.