Negative power supply

Claim 2

A negative power supply for generating and supplying a regulated negative potential to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure, said negative power supply comprising: clock means (14) for generating a plurality of clock signals; charge pumping means (12) responsive to an external power supply potential (VCC) and to said clock signals for generating a high negative voltage; said charge pumping means being formed of a plurality of charge pump stages (401-404); cancellation means coupled to each stage of said charge pumping means for effectively canceling out voltage drops due to threshold voltages in said charge pumping means; negative well means (20) coupled to said plurality of charge pumping stages for preventing initially the operation of a certain number of said plurality of charge pump stages during erasure; and regulation means (16) responsive to said high negative voltage and a reference potential for generating a negative comparator signal which is either at a high level so as to allow said charge pumping means to increase said high negative voltage or is at a low level so as to decrease said high negative voltage and for generating said regulated negative potential to be independent of the supply potential (VCC).

Claim 3

A negative power supply as claimed in claim 1, wherein each of said plurality of charge pump stages is comprised of a P-channel pass transistor and a first coupling capacitor, said pass transistor having its source connected to an input node, its drain connected to an output node and its gate connected to an internal node, said coupling capacitor having its one side connected to the output node and its other side connected to receive a first one of said plurality of clock signals.

Claim 4

A negative power supply as claimed in claim 2, wherein each of said cancellation means is comprised of a P-channel initialization transistor, a P-channel precharge transistor, and a second coupling capacitor, said initialization transistor having its drain and gate connected to the input node and its source connected to the output node, said pre-charge transistor having its source connected to the input node, its gate connected to the output node, and its drain connected to the internal node, said second coupling capacitor having its one side also connected to the internal node and its other side connected to receive a second one of said plurality of clock signals.

Claim 5

A negative power supply as claimed in claim 1, wherein said high negative voltage is approximately -12 volts.

Claim 6

A negative power supply as claimed in claim 1, wherein said regulated negative potential is approximately -10 volts.

Claim 7

A negative power supply as claimed in claim 1, wherein said negative well means generates a negative well signal which is maintained at the power supply potential (VCC) for a short time at the beginning of the erasure and is then allowed to go to 0 volts.

Claim 8

A negative power supply as claimed in claim 1, wherein said regulator means is comprised of a differential comparator having a non-inverting input, an inverting input, and an output and a P-channel pull-up transistor, said differential comparator having its noninverting input coupled to said high negative voltage, its inverting input coupled to the reference potential, and its output coupled to the gate of said P-channel pull-up transistor, the source of said P-channel pull-up transistor having its source connected to the power supply potential (VCC), the drain of said P-channel pull-up transistor being coupled to said charge pumping means to provide said regulated negative potential.

Claim 9

A negative power supply as claimed in claim 1, further comprising means coupled to said negative well means for generating a protection signal to provide protection of the oxide of a pull-up device in said negative well means.

Claim 10

A negative power supply as claimed in claim 1, further comprising array circuit means for generating an array signal which is at a relatively low positive voltage during flash erasure and is supplied to source regions of the selected memory cells.

Claim 11

In an array of flash EEPROM memory cells formed on the substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a plurality of bit lines extending along respective columns, where each memory cell includes an N-type source region coupled to the common source line, a control gate, a floating gate, a channel region and an N-type drain region coupled to a respective one of the bit lines, where each memory cell is erasable predominately by tunneling electrons from its floating gate to its source region, and a negative power supply for generating and supplying a regulated negative potential to control gates of selected memory cells via the wordlines during flash erasure, said negative potential supply comprising: clock means (14) for generating a plurality of clock signals; charge pumping means (12) responsive to an external power supply potential (VCC) and to said clock signals for generating a high negative voltage; said charge pumping means being formed of a plurality of charge pump stages (401-402); cancellation means coupled to each stage of said charge pumping means for effectively canceling out voltage drops due to threshold voltages in said charge pumping means; negative well means (20) coupled to said plurality of charge pumping stages for preventing initially the operation of a certain number of said plurality of charge pump stages during erasure; and regulation means (16) responsive to said high negative voltage and a reference potential for generating a negative comparator signal which is either at a high level so as to allow said charge pumping means to increase said high negative voltage or is at a low level so as to decrease said high negative voltage and for generating said regulated negative potential to be independent of the supply potential (VCC).

Claim 12

In an array of flash EEPROM memory cells formed on the substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a plurality of bit lines extending along respective columns, where each memory cell includes an N-type source region coupled to the common source line, a control gate, a floating gate, a channel region and an N-type drain region coupled to a respective one of the bit lines, where each memory cell is erasable predominately by tunneling electrons from its floating gate to its source region, and a negative power supply for generating and supplying a regulated negative potential to control gates of selected memory cells via the wordlines during flash erasure, said negative potential supply comprising: clock means (14) for generating a plurality of clock signals; charge pumping means (12) responsive to an external power supply potential (VCC) and to said clock signals for generating a high negative voltage; said charge pumping means being formed of a plurality of charge pump stages (401-402); cancellation means coupled to each stage of said charge pumping means for effectively canceling out voltage drops due to threshold voltages in said charge pumping means; negative well means (20) coupled to said plurality of charge pumping stages for preventing initially the operation of a certain number of said plurality of charge pump stages during erasure; and regulation means (16) responsive to said high negative voltage and a reference potential for generating a negative comparator signal which is either at a high level so as to allow said charge pumping means to increase said high negative voltage or is at a low level so as to decrease said high negative voltage and for generating said regulated negative potential to be independent of the supply potential (VCC).

Claim 13

In an array of flash EEPROM memory cells as claimed in claim 10, wherein each of said plurality of charge pump stages is comprised of a P-channel pass transistor and a first coupling capacitor, said pass transistor having its source connected to an input node, its drain connected to an output node and its gate connected to an internal node, said coupling capacitor having its one side connected to the output node and its other side connected to receive a first one of said plurality of clock signals.

Claim 14

In an array of flash EEPROM memory cells as claimed in claim 11, wherein each of said cancellation means is comprised of a P-channel initialization transistor, a P-channel pre-charge transistor, and a second coupling capacitor, said initialization transistor having its drain and gate connected to the input node and its source connected to the output node, said pre-charge transistor having its source connected to the input node, its gate connected to the output node, and its drain connected to the internal node, said second coupling capacitor having its one side also connected to the internal node and its other side connected to receive a second one of said plurality of clock signals.

Claim 15

In an array of flash EEPROM memory cells as claimed in claim 10, wherein said high negative voltage is approximately -12 volts.

Claim 16

In an array of flash EEPROM memory cells as claimed in claim 10, wherein said regulated negative potential is approximately -10 volts.

Claim 17

In an array of flash EEPROM memory cells as claimed in claim 10, wherein said negative well means generates a negative well signal which is maintained at the power supply potential (VCC) for a short time at the beginning of the erasure and is then allowed to go to 0 volts.

Claim 18

In an array of flash EEPROM memory cells as claimed in claim 10, wherein said regulator means is comprised of a differential comparator having a non-inverting input, an inverting input, and an output and a P-channel pull-up transistor, said differential comparator having its non-inverting input coupled to said high negative voltage, its inverting input coupled to the reference potential, and its output coupled to the gate of said P-channel pull-up transistor, the source of said P-channel pull-up transistor having its source connected to the power supply potential (VCC), the drain of said P-channel pull-up transistor being coupled to said charge pumping means to provide said regulated negative potential.

Claim 19

In an array of flash EEPROM memory cells as claimed in claim 10, further comprising means coupled to said negative well means for generating a protection signal to provide protection of the oxide of a pull-up device in said negative well means.

Claim 20

In an array of flash EEPROM memory cells as claimed in claim 10, further comprising array circuit means for generating an array signal which is at a relatively low positive voltage during flash erasure and is supplied to source regions of the selected memory cells.

Claim 21

A negative power supply for generating and supplying a regulating negative potential to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure, said negative power supply comprising: charge pumping means (12) responsive to an external power supply potential (VCC) and to clock signals for generating a high negative voltage; said cancellation means coupled to said charge pumping means for effectively canceling out voltage drops due to threshold voltages in said charge pumping means; and regulation means (16) responsive to said high negative voltage and a reference potential for generating a negative comparator signal which is either at a high level so as to allow said charge pumping means to increase said high negative voltage or is at a low level so as to decrease said high negative voltage and for generating said regulated negative potential to be independent of the supply potential (VCC).

Claim 22

A negative power supply for generating and supplying a regulating negative potential to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure, said negative power supply comprising: charge pumping means (12) responsive to an external power supply potential (VCC) and to clock signals for generating a high negative voltage; said cancellation means coupled to said charge pumping means for effectively canceling out voltage drops due to threshold voltages in said charge pumping means; and regulation means (16) responsive to said high negative voltage and a reference potential for generating a negative comparator signal which is either at a high level so as to allow said charge pumping means to increase said high negative voltage or is at a low level so as to decrease said high negative voltage and for generating said regulated negative potential to be independent of the supply potential (VCC).