US5693568A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reverse damascene via structures
Assignee: GlobalFoundries Inc
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Filing: 1995-12-14
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Granted: 1997-12-02
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Expires: 2015-12-14
Abstract
Abstract A reliable interconnection pattern is formed by depositing first and second conductive layers, etching to form a conductive pattern in the first conductive layer and etching to form an interconnection comprising a portion of the second conductive layer. Advantageously, the need to form openings in dielectric layers, and filling them with barrier materials and plugs, is avoided along with their attendant disadvantages. The resulting semiconductor device exhibits improved reliability, higher operating speeds and an improved signal-to-noise ratio.
Inventors
- 👤 Yowjuang W. Liu
- 👤 Kuang-Yeh Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:54
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10W20/0633; H10W20/069; H10W20/0693
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
142 words
A method of manufacturing a semiconductor device, which method comprises: depositing a plurality of sequential dielectric and conductive layers on a semiconductor substrate, each conductive layer comprising at least one conductive pattern; and forming an interconnection electrically connecting a conductive pattern of an upper conductive layer and a conductive pattern of a lower conductive layer by: depositing a first lower conductive layer; depositing a second conductive layer on and in electrical contact with the first conductive layer; etching the first lower conductive layer to form a conductive pattern comprising a conductive line; and etching the second conductive layer, after etching the first lower conductive layer, to form at least a portion of the interconnection from the remaining second conductive layer, wherein the width of the portion of the interconnection is less than the width of an underlying electrically connected etched conductive line.
Claim 2
Independent Claim
142 words
A method of manufacturing a semiconductor device, which method comprises: depositing a plurality of sequential dielectric and conductive layers on a semiconductor substrate, each conductive layer comprising at least one conductive pattern; and forming an interconnection electrically connecting a conductive pattern of an upper conductive layer and a conductive pattern of a lower conductive layer by: depositing a first lower conductive layer; depositing a second conductive layer on and in electrical contact with the first conductive layer; etching the first lower conductive layer to form a conductive pattern comprising a conductive line; and etching the second conductive layer, after etching the first lower conductive layer, to form at least a portion of the interconnection from the remaining second conductive layer, wherein the width of the portion of the interconnection is less than the width of an underlying electrically connected etched conductive line.
Claim 3
Dependent Claim
42 words
The method according to claim 1, further comprising: depositing a layer of etch stop material on and in electrical contact with the first lower conductive layer; and depositing the second conductive layer on and in electrical contact with the etch stop material.
Claim 4
Dependent Claim
21 words
The method according to claim 1, wherein the etch stop material comprises tungsten, titanium, an alloy thereof, or a nitride thereof.
Claim 5
Dependent Claim
31 words
The method according to claim 1, wherein the interconnection comprises a metal selected from the group consisting of aluminum, aluminum-based alloys, copper, copper-based alloys, gold, gold-based alloys, silver, and silver-based alloys.
Claim 6
Dependent Claim
21 words
The method according to claim 1, wherein the first lower conductive layer and the second conductive layer comprise the same metal.
Claim 7
Dependent Claim
26 words
The method according to claim 5, wherein the metal is selected from the group consisting of aluminum, aluminum-based alloys, copper, copper-based alloys, silver and silver-based alloys.
Claim 8
Dependent Claim
20 words
The method according to claim 1, wherein the second conductive layer is deposited coextensive with the first lower conductive layer.
Claim 9
Independent Claim
112 words
A method of manufacturing a semiconductor device, which method comprises: depositing a first dielectric interlayer on a semiconductor substrate; depositing a first lower conductive layer on the first dielectric interlayer; depositing a second conductive layer on and in electrical contact with the first conductive layer; etching the first and second conductive layers to form at least one conductive pattern; forming a second dielectric interlayer; etching the second conductive layer, after forming the second dielectric interlayer, without substantially etching the first lower conductive layer to define at least a portion of an interconnection comprising remaining second conductive layer on and in electrical contact with a conductive pattern of the first lower conductive layer.
Claim 10
Independent Claim
112 words
A method of manufacturing a semiconductor device, which method comprises: depositing a first dielectric interlayer on a semiconductor substrate; depositing a first lower conductive layer on the first dielectric interlayer; depositing a second conductive layer on and in electrical contact with the first conductive layer; etching the first and second conductive layers to form at least one conductive pattern; forming a second dielectric interlayer; etching the second conductive layer, after forming the second dielectric interlayer, without substantially etching the first lower conductive layer to define at least a portion of an interconnection comprising remaining second conductive layer on and in electrical contact with a conductive pattern of the first lower conductive layer.
Claim 11
Dependent Claim
101 words
The method according to claim 8, further comprising: depositing a third conductive layer on the second dielectric interlayer and on and in electrical contact with an exposed interconnection; depositing a fourth conductive layer on and in electrical contact with the third conductive layer; etching the third and fourth conductive layers to form at least one conductive pattern; depositing a third dielectric interlayer; etching the fourth conductive layer without substantially etching the third conductive layer to define at least a portion of an interconnection comprising the remaining fourth conductive layer in electrical contact with a conductive pattern of the third conductive layer.
Claim 12
Dependent Claim
46 words
The method according to claim 9, further comprising: forming a third dielectric interlayer; depositing a fifth conductive layer on the third dielectric interlayer and on and in electrical contact with an exposed interconnection; and etching the fifth conductive layer to form at least one conductive pattern.
Claim 13
Dependent Claim
13 words
The method according to claim 10, further comprising depositing a topside dielectric layer.
Claim 14
Dependent Claim
39 words
The method according to claim 8, wherein the first lower conductive layer and second conductive layer comprises the same metal selected from the group consisting of aluminum, aluminum-based alloys, gold, gold-based alloys, silver, silver-based alloys, copper and copper-based alloys.
Claim 15
Dependent Claim
42 words
The method according to claim 8, further comprising: depositing a layer of etch stop material on and in electrical contact with the first lower conductive layer; and depositing the second conductive layer on and in electrical contact with the etch stop layer.
Claim 16
Dependent Claim
20 words
The method according to claim 13, wherein the etch stop comprises tungsten, titanium, an alloy thereof or a nitride thereof.
Claim 17
Dependent Claim
48 words
The method according to claim 8, further comprising: depositing a layer of dielectric material after etching the first and second conductive layers and prior to etching the second conductive layer; and planarizing to expose a remaining portion of the second conductive layer and form the second dielectric interlayer.
Claim 18
Dependent Claim
27 words
The method according to claim 15, further comprising applying a photomask prior to etching the second conductive layer to define at least a portion of an interconnection.
Claim 19
Dependent Claim
31 words
The method according to claim 8, further comprising: depositing a dielectric material after etching the second conductive layer to fill in the second dielectric interlayer; and planarizing to expose an interconnection.
Claim 20
Dependent Claim
41 words
The method according to claim 9, further comprising: depositing a layer of etch stop material on and in electrical contact with the third conductive layer; and depositing the fourth conductive layer on and in electrical contact with the etch stop layer.
Claim 21
Dependent Claim
21 words
The method according to claim 18, wherein the etch stop layer comprises tungsten, titanium, an alloy thereof or a nitride thereof.
Claim 22
Dependent Claim
80 words
The method according to claim 8, further comprising: forming at least one active region in the semiconductor substrate prior to depositing the first dielectric interlayer; forming an opening in the first dielectric interlayer exposing a portion of an active region in the semiconductor substrate prior to depositing the first lower conductive layer; filling the opening with conductive material; and depositing the first lower conductive layer on the first dielectric layer in electrical contact with the conductive material in the opening.
Claim 23
Dependent Claim
38 words
The method according to claim 1, comprising etching the second conductive layer to form a portion of the interconnection having a side surface substantially vertically aligned with a side surface of the underlying electrically connected etched conductive line.
Claim 24
Dependent Claim
27 words
The method according to claim 8, wherein the width of the portion of the interconnection is less than the width of an underlying electrically connected conductive line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-01 | 2001-06-02 | 2001-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-01 | 2005-06-02 | 2005-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-01 | 2009-06-02 | 2009-12-02 | $7700.00 | Window Closed / Lapsed |