Planar metal interconnection for a VLSI device

Claim 1

A method of forming a contact or interconnect for a semiconductor integrated circuit device, comprising: forming first and pillar layers of electrically conducting material on a face of the semiconductor forming a pillar masking pad on said pillar layer; photolithographically patterning and etching the pillar and first layers to the dimension of a first lead confining said pillar masking pad; and etching the pillar layer to form a pillar.

Claim 2

A method of forming a contact or interconnect for a semiconductor integrated circuit device, comprising: forming first and pillar layers of electrically conducting material on a face of the semiconductor forming a pillar masking pad on said pillar layer; photolithographically patterning and etching the pillar and first layers to the dimension of a first lead confining said pillar masking pad; and etching the pillar layer to form a pillar.

Claim 14

A method for forming a contact or interconnect for an integrated circuit device comprising: forming a conductive first lead layer and a conductive pillar layer on a face of a substrate; forming a pillar masking pad on said pillar layer; photolithographically patterning the pillar layer to first lead dimensions confining the pillar masking pad; etching the pillar layer and the first lead layer to respectively define a pillar and a first lead.

Claim 15

A method for forming a contact or interconnect for an integrated circuit device comprising: forming a conductive first lead layer and a conductive pillar layer on a face of a substrate; forming a pillar masking pad on said pillar layer; photolithographically patterning the pillar layer to first lead dimensions confining the pillar masking pad; etching the pillar layer and the first lead layer to respectively define a pillar and a first lead.

Claim 21

A method of interconnecting different metal layers through an intermediate insulating layer, comprising the steps of: forming first and pillar layers on the face of a semiconductor each with a bottom deposit of barrier metal and a top deposit of conducting metal and an upper layer of barrier metal atop said pillar layer; photolithographically masking and etching said upper layer of barrier metal to form a pillar masking pad; photolithographically masking and etching said pillar layer and barrier metal under the pillar layer to dimensions of a first lead; etching exposed portions of the pillar layer and first lead layer to form a pillar and first lead; depositing a layer of dielectric sufficiently thick to cover said pillar interconnection and said first level lead; applying a layer of photoresist so as to form a planar surface over said pillar and said first level lead; etching back the photoresist and dielectric so as to expose a top portion of said pillar; and depositing another layer of conducting material over said pillar and dielectric material to form a second level lead.

Claim 22

A method of interconnecting different metal layers through an intermediate insulating layer, comprising the steps of: forming first and pillar layers on the face of a semiconductor each with a bottom deposit of barrier metal and a top deposit of conducting metal and an upper layer of barrier metal atop said pillar layer; photolithographically masking and etching said upper layer of barrier metal to form a pillar masking pad; photolithographically masking and etching said pillar layer and barrier metal under the pillar layer to dimensions of a first lead; etching exposed portions of the pillar layer and first lead layer to form a pillar and first lead; depositing a layer of dielectric sufficiently thick to cover said pillar interconnection and said first level lead; applying a layer of photoresist so as to form a planar surface over said pillar and said first level lead; etching back the photoresist and dielectric so as to expose a top portion of said pillar; and depositing another layer of conducting material over said pillar and dielectric material to form a second level lead.

Claim 26

A method of forming a conductive interconnect on a face of a semiconductor body, comprising the steps of: applying a bottom barrier layer to said face, applying a first conductive layer to said face, applying a first barrier layer to said face over said first conductive layer, applying a second conductive layer to said face over said first barrier layer, then applying a second barrier layer to said face over said second conductive layer; photolithographically masking and selectively removing said second barrier layer to leave a pillar mask on said face, then selectively removing said second conductive layer and said first barrier layer to leave a first conductive strip extending over said face to define a first lead area; etching said face using said second and first barrier layers as masks and said second and bottom barrier layers as etch stops to thereby remove said second conductive layer except under said strip area, leaving a pillar and a first lead; applying an insulating coating to said face to cover the pillar and the conductive strip and to cover other areas of said face not covered by the conductive strip to produce an uneven surface with raised areas above the pillar and conductive strip; applying to said face a coating of a filler material which flows to create a plane surface above raised areas and other areas of said face; etching said face with an etchant which removes said filler material at about the same rate as it removes said insulator coating until the filler material has been removed and the top of the pillar has been exposed, leaving a substantially plane top surface; then applying another conductive strip to said face contacting said pillar.

Claim 27

A method of forming a conductive interconnect on a face of a semiconductor body, comprising the steps of: applying a bottom barrier layer to said face, applying a first conductive layer to said face, applying a first barrier layer to said face over said first conductive layer, applying a second conductive layer to said face over said first barrier layer, then applying a second barrier layer to said face over said second conductive layer; photolithographically masking and selectively removing said second barrier layer to leave a pillar mask on said face, then selectively removing said second conductive layer and said first barrier layer to leave a first conductive strip extending over said face to define a first lead area; etching said face using said second and first barrier layers as masks and said second and bottom barrier layers as etch stops to thereby remove said second conductive layer except under said strip area, leaving a pillar and a first lead; applying an insulating coating to said face to cover the pillar and the conductive strip and to cover other areas of said face not covered by the conductive strip to produce an uneven surface with raised areas above the pillar and conductive strip; applying to said face a coating of a filler material which flows to create a plane surface above raised areas and other areas of said face; etching said face with an etchant which removes said filler material at about the same rate as it removes said insulator coating until the filler material has been removed and the top of the pillar has been exposed, leaving a substantially plane top surface; then applying another conductive strip to said face contacting said pillar.