Pillar alignment and formation process

Claim 1

A method of interconnecting metal layers through an intermediate insulating layer, said method comprising the steps of: forming first and pillar layers of electrically conducting material on a substrate having an aligning structure thereon; forming a first layer pattern in said first layer and a pillar pattern in said pillar layer, said first layer pattern being aligned with said aligning structure and said pillar pattern being aligned with said first layer pattern; depositing an insulating layer over said first and pillar layers; removing portions of said insulating layer to expose a portion of said pillar layer; and depositing a second layer of conducting material over said pillar and insulating layers to form a second layer pattern so that said pillar layer connects said first layer to said second layer.

Claim 2

A method of interconnecting metal layers through an intermediate insulating layer, said method comprising the steps of: forming first and pillar layers of electrically conducting material on a substrate having an aligning structure thereon; forming a first layer pattern in said first layer and a pillar pattern in said pillar layer, said first layer pattern being aligned with said aligning structure and said pillar pattern being aligned with said first layer pattern; depositing an insulating layer over said first and pillar layers; removing portions of said insulating layer to expose a portion of said pillar layer; and depositing a second layer of conducting material over said pillar and insulating layers to form a second layer pattern so that said pillar layer connects said first layer to said second layer.

Claim 8

A method of interconnecting first and second conductive layers through an intermediate insulating layer, said method comprising the steps of: forming said first conductive layer overlying a substrate which has an alignment structure thereon, a conductive pillar layer overlying said first layer, and a barrier layer overlying said pillar layer; removing portions of said pillar and barrier layers to define a first layer pattern in said pillar and barrier layers, said first layer pattern being aligned with said alignment structure; removing portions of said barrier layer to define a pillar pattern in said barrier layer, said pillar pattern being aligned with said first layer pattern; transferring said first layer pattern to said first layer and said pillar pattern to said pillar layer; forming said insulating layer overlying said first layer; and forming said second conductive layer overlying said insulating and pillar layers.

Claim 9

A method of interconnecting first and second conductive layers through an intermediate insulating layer, said method comprising the steps of: forming said first conductive layer overlying a substrate which has an alignment structure thereon, a conductive pillar layer overlying said first layer, and a barrier layer overlying said pillar layer; removing portions of said pillar and barrier layers to define a first layer pattern in said pillar and barrier layers, said first layer pattern being aligned with said alignment structure; removing portions of said barrier layer to define a pillar pattern in said barrier layer, said pillar pattern being aligned with said first layer pattern; transferring said first layer pattern to said first layer and said pillar pattern to said pillar layer; forming said insulating layer overlying said first layer; and forming said second conductive layer overlying said insulating and pillar layers.

Claim 15

A method of forming a pillar in a semiconductor device having an alignment structure thereon, a first barrier layer overlying said alignment structure, a bottom conductive layer overlying said first barrier layer, the second barrier layer overlying said bottom conductive layer, a top conductive layer overlying said second barrier layer, and a third barrier layer overlying said top conductive layer, said method comprising the steps of: defining a lead pattern in said third barrier layer, said top conductive layer, and said second barrier layer, said lead pattern being laterally positioned within a predetermined tolerance of said alignment structure; defining a pillar pattern in said third barrier layer said pillar pattern being laterally positioned within said predetermined tolerance of said lead pattern; simultaneously etching portions of said top and bottom conductive layers using an etchant which etches entirely through said conductive layers without etching through said barrier layers; and simultaneously etching portions of said first, second, and third barrier layers using said top and bottom conductive layers as etch stops.

Claim 16

A method of forming a pillar in a semiconductor device having an alignment structure thereon, a first barrier layer overlying said alignment structure, a bottom conductive layer overlying said first barrier layer, the second barrier layer overlying said bottom conductive layer, a top conductive layer overlying said second barrier layer, and a third barrier layer overlying said top conductive layer, said method comprising the steps of: defining a lead pattern in said third barrier layer, said top conductive layer, and said second barrier layer, said lead pattern being laterally positioned within a predetermined tolerance of said alignment structure; defining a pillar pattern in said third barrier layer said pillar pattern being laterally positioned within said predetermined tolerance of said lead pattern; simultaneously etching portions of said top and bottom conductive layers using an etchant which etches entirely through said conductive layers without etching through said barrier layers; and simultaneously etching portions of said first, second, and third barrier layers using said top and bottom conductive layers as etch stops.