Patent US5693550A successfully refreshed from Google Patents.
US5693550A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating self-aligned silicide device using CMP
Assignee: NEC Electronics Corp
•
Filing: 1996-10-31
•
Granted: 1997-12-02
•
Expires: 2016-10-31
Abstract
Abstract A titanium film and a polysilicon film are caused to react with each other to produce a TiSi 2 layer of silicide. Thereafter, an upper end of a side wall is polished off to remove an electrically conductive TiSix layer which has been formed on the upper end of the side wall at the same time that the silicide has been formed. It is thus possible to keep low the layer resistance of the silicide layer on a gate electrode and a source-drain region and to prevent the source-drain region and the gate electrode from being short-circuited.
Inventors
- 👤 Kozi Torii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/011; H10D30/0212
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
124 words
A method of fabricating a semiconductor device having a gate electrode and a source-drain region on a semiconductor substrate, comprising the steps of: forming a gate oxide film and a gate electrode on a semiconductor substrate; thereafter, forming a side wall on a side surface of said gate electrode; thereafter, forming a self-aligned source-drain region while using said gate electrode and said side wall as a mask; thereafter, forming a refractory metal film on an entire surface of said semiconductor substrate; thereafter, causing said refractory metal film and silicon to react with each other, producing a silicide; thereafter, removing a portion of said refractory metal film which has not reacted with said silicon; and thereafter, polishing off an upper end of said side wall.
Claim 2
Independent Claim
124 words
A method of fabricating a semiconductor device having a gate electrode and a source-drain region on a semiconductor substrate, comprising the steps of: forming a gate oxide film and a gate electrode on a semiconductor substrate; thereafter, forming a side wall on a side surface of said gate electrode; thereafter, forming a self-aligned source-drain region while using said gate electrode and said side wall as a mask; thereafter, forming a refractory metal film on an entire surface of said semiconductor substrate; thereafter, causing said refractory metal film and silicon to react with each other, producing a silicide; thereafter, removing a portion of said refractory metal film which has not reacted with said silicon; and thereafter, polishing off an upper end of said side wall.
Claim 3
Dependent Claim
12 words
A method according to claim 1, wherein said side wall contains silicon.
Claim 4
Independent Claim
124 words
A method of fabricating a semiconductor device having a gate electrode and a source-drain region on a semiconductor substrate, comprising the steps of: forming a gate oxide film and a gate electrode on a semiconductor substrate; thereafter, forming a side wall on a side surface of said gate electrode; thereafter, forming a self-aligned source-drain region while using said gate electrode and said side wall as a mask; thereafter, forming a refractory metal film on an entire surface of said semiconductor substrate; thereafter, causing said refractory metal film and silicon to react with each other, producing a silicide; thereafter, polishing off an upper end of said side wall; and thereafter, removing a portion of said refractory metal film which has not reacted with said silicon.
Claim 5
Independent Claim
124 words
A method of fabricating a semiconductor device having a gate electrode and a source-drain region on a semiconductor substrate, comprising the steps of: forming a gate oxide film and a gate electrode on a semiconductor substrate; thereafter, forming a side wall on a side surface of said gate electrode; thereafter, forming a self-aligned source-drain region while using said gate electrode and said side wall as a mask; thereafter, forming a refractory metal film on an entire surface of said semiconductor substrate; thereafter, causing said refractory metal film and silicon to react with each other, producing a silicide; thereafter, polishing off an upper end of said side wall; and thereafter, removing a portion of said refractory metal film which has not reacted with said silicon.
Claim 6
Dependent Claim
12 words
A method according to claim 3, wherein said side wall contains silicon.
References Cited (Backward Citations)
US5286678A
Cited
US5567651A
Cited
US5607884A
Cited
US5472894A
Cited
US5491099A
Cited
US5576227A
Cited
US5472897A
Cited
US5508212A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-01 | 2001-06-02 | 2001-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-01 | 2005-06-02 | 2005-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-01 | 2009-06-02 | 2009-12-02 | $7700.00 | Window Closed / Lapsed |