Method of manufacturing a LDD transistor in a semiconductor device

Claim 1

A method of manufacturing a transistor in a semiconductor device, comprising the steps of: growing an oxide layer on a silicon substrate having an N-well having a first doping concentration; forming a N + region within said silicon substrate having a higher doping concentration than said first doping concentration of said N-well; removing said oxide layer and forming a first BSG layer on a resulting structure after removing said oxide layer; forming a P - layer on said N + region; removing said first BSG layer and sequentially forming a gate oxide layer and a polysilicon layer on a resulting structure after removing said first BSG layer; implanting P conductivity type impurity ions into said polysilicon layer and sequentially patterning said polysilicon layer and said oxide layer, thereby forming a gate electrode; forming spacers on opposing side walls of said gate electrode; depositing a second BSG layer on a resulting structure after forming said spacers; implanting P conductivity type impurity ions into said silicon substrate, thereby forming a P + junction region; performing a rapid thermal annealing process; and removing said second BSG layer.

Claim 2

A method of manufacturing a transistor in a semiconductor device, comprising the steps of: growing an oxide layer on a silicon substrate having an N-well having a first doping concentration; forming a N + region within said silicon substrate having a higher doping concentration than said first doping concentration of said N-well; removing said oxide layer and forming a first BSG layer on a resulting structure after removing said oxide layer; forming a P - layer on said N + region; removing said first BSG layer and sequentially forming a gate oxide layer and a polysilicon layer on a resulting structure after removing said first BSG layer; implanting P conductivity type impurity ions into said polysilicon layer and sequentially patterning said polysilicon layer and said oxide layer, thereby forming a gate electrode; forming spacers on opposing side walls of said gate electrode; depositing a second BSG layer on a resulting structure after forming said spacers; implanting P conductivity type impurity ions into said silicon substrate, thereby forming a P + junction region; performing a rapid thermal annealing process; and removing said second BSG layer.