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US5434440A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device and method of manufacturing the same

Assignee: Toshiba Corp
•
Filing: 1993-05-28
•
Granted: 1995-07-18
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Expires: 2013-05-28
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Abstract

Abstract A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5×10 18 cm -3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 μm. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.

Inventors

  • 👤 Takashi Yoshitomi
  • 👤 Masanobu Saito
  • 👤 Hisayo Momose
  • 👤 Hiroshi Iwai
  • 👤 Yukihiro Ushiku
  • 👤 Mizuki Ono
  • 👤 Yasushi Akasaka
  • 👤 Hideaki Nii
  • 👤 Satoshi Matsuda
  • 👤 Yasuhiro Katsumata

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 03:05
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/022; H10D30/0223; H10D30/0227; H10D30/027; H10D30/0275; H10D30/60; H10D30/601; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01326; H10D64/015; H10D64/021; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171; H10P76/00; H10P76/40; H10P76/408; H10P76/4088; Y; Y10; Y10S; Y10S257/00; Y10S257/90; Y10S438/00; Y10S438/965

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 179 words
A semiconductor device comprising: a gate electrode formed on a region of a semiconductor substrate of a first conductivity type, said gate electrode region surrounded by a device isolation region; a channel formation region immediately below said gate electrode and within said semiconductor substrate; and a source region and a drain region, each being formed of a second conductivity type impurity diffused region, said second conductivity type impurity diffused region being comprised of (1) a first diffused layer adjacent said channel formation region and (2) a second diffused layer positioned between said first diffused layer and said channel formation region, both said first and said second diffused layers being within said semiconductor substrate, said second diffused layer being formed so that it is shallower than said first diffused layer, the distribution in a depth direction of carriers of said second diffused layer having a profile in which the concentration is more than 5×10 18 cm -3 at the peak concentration and is equal to a carrier concentration of said semiconductor substrate at a depth of less than 0.04 μm.
Claim 2
Dependent Claim 179 words
A semiconductor device comprising: a gate electrode formed on a region of a semiconductor substrate of a first conductivity type, said gate electrode region surrounded by a device isolation region; a channel formation region immediately below said gate electrode and within said semiconductor substrate; and a source region and a drain region, each being formed of a second conductivity type impurity diffused region, said second conductivity type impurity diffused region being comprised of (1) a first diffused layer adjacent said channel formation region and (2) a second diffused layer positioned between said first diffused layer and said channel formation region, both said first and said second diffused layers being within said semiconductor substrate, said second diffused layer being formed so that it is shallower than said first diffused layer, the distribution in a depth direction of carriers of said second diffused layer having a profile in which the concentration is more than 5×10 18 cm -3 at the peak concentration and is equal to a carrier concentration of said semiconductor substrate at a depth of less than 0.04 μm.

References Cited (Backward Citations)

US4356623A Cited
US4356623B1 Cited
JPS60134469A Cited
JPS6143477A Cited
JPS61154172A Cited
JPS61156858A Cited
US5061649A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-07-17 1999-01-16 1999-07-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-07-17 2003-01-16 2003-07-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-07-17 2007-01-16 2007-07-18 $7700.00 Window Closed / Lapsed

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