US5338698A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating an ultra-short channel field effect transistor
Assignee: International Business Machines Corp
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Filing: 1992-12-18
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Granted: 1994-08-16
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Expires: 2012-12-18
Abstract
Abstract An ultra-short channel field effect transistor provides a combination of a shallow junction for injection of carriers into a conduction channel and a Schottky barrier below the shallow junction with a lowered barrier height to reduce the depletion region and punch-through effects. A preferred method of fabricating this structure includes both etching and metal deposition selectively on only semiconductor material, allowing use of only a single patterning step with registration tolerances comparable to channel length while allowing extremely high integration density.
Inventors
- 👤 Seshadri Subbanna
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:09
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/64; H10D64/647; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0277; H10D62/00; H10D62/01; H10D62/021; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/378
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
168 words
A method of fabricating a field effect transistor including the steps of forming blanket layers of a gate oxide, a gate electrode material and an oxide overlying said layer of gate electrode material, over a layer of semiconductor material of a first conductivity type having shallow isolation trenches formed therein, patterning said blanket layers to remove said blanket layers except at a generally centered location between a pair of said shallow isolation trenches, remaining portions of said blanket layers being laterally separated from edges of said shallow isolation trenches, implanting an impurity of a second conductivity type to a first depth between edges of said remaining portions of said blanket layers and said shallow trenches, forming sidewall spacers on said remaining portions of said blanket layers, removing material from a surface of said layer of semiconductor material to a second depth, said second depth exceeding said first depth, between edges of said shallow trenches of said sidewall spacers, and depositing metal in volumes formed by said removing step.
Claim 2
Independent Claim
168 words
A method of fabricating a field effect transistor including the steps of forming blanket layers of a gate oxide, a gate electrode material and an oxide overlying said layer of gate electrode material, over a layer of semiconductor material of a first conductivity type having shallow isolation trenches formed therein, patterning said blanket layers to remove said blanket layers except at a generally centered location between a pair of said shallow isolation trenches, remaining portions of said blanket layers being laterally separated from edges of said shallow isolation trenches, implanting an impurity of a second conductivity type to a first depth between edges of said remaining portions of said blanket layers and said shallow trenches, forming sidewall spacers on said remaining portions of said blanket layers, removing material from a surface of said layer of semiconductor material to a second depth, said second depth exceeding said first depth, between edges of said shallow trenches of said sidewall spacers, and depositing metal in volumes formed by said removing step.
Claim 3
Dependent Claim
33 words
A method as recited in claim 1, including the further steps of removing said oxide overlying said layer of gate electrode material, and depositing a layer of material of said gate electrode material.
Claim 4
Dependent Claim
20 words
A method as recited in claim 1, wherein said step of forming sidewall spacers includes forming a layer of oxide.
Claim 5
Dependent Claim
20 words
A method as recited in claim 1, wherein said step of forming sidewall spacers includes forming a layer of nitride.
Claim 6
Dependent Claim
22 words
A method as recited in claim 1, wherein said step of depositing metal includes selective deposition of metal on semiconductor material surfaces.
Claim 7
Dependent Claim
20 words
A method as recited in claim 1, wherein said first depth of said implanting step is less than 50 nm.
Claim 8
Dependent Claim
14 words
A method as recited in claim 6 wherein said second depth is 100 nm.
Claim 9
Dependent Claim
21 words
A method as recited in claim 1, wherein said step of depositing metal includes the step of forming a metal silicide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-15 | 1998-02-14 | 1998-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-15 | 2002-02-14 | 2002-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-15 | 2006-02-14 | 2006-08-16 | $7700.00 | Window Closed / Lapsed |