Voltage control circuit for a dual voltage bus computer system

Claim 2

A computer system comprising: a circuit element powered by both a first steady state voltage and a second steady state voltage different from the first steady state voltage; a first bus coupled to the circuit element which provides the first steady state voltage; a second bus coupled to the circuit element which provides the second steady state voltage; and a voltage control circuit coupled to the first and second buses which prevents damage to the circuit element by preventing an instantaneous voltage on the first bus from exceeding another instantaneous voltage on the second bus during power removal from the computer system and during a short circuit on the second bus, wherein the voltage control circuit includes a comparison circuit coupled to the first and second buses which compares the instantaneous voltage on the first bus with the instantaneous voltage on the second bus, and a switch controlled by the comparison circuit for drawing current from the first bus to reduce the voltage on the first bus to remain below the voltage on the second bus when the voltage on second bus decreases.

Claim 3

The computer system as recited in claim 1, wherein the voltage control circuit further comprises: a voltage gap determining circuit coupled between the second bus and the comparison circuit which provides a reference voltage to the comparison circuit that is a predetermined fraction of the instantaneous voltage on the second bus.

Claim 4

The computer system as recited in claim 2, wherein the first bus has a steady state voltage of 3.3 volts and the second bus has a steady state voltage of 5 volts, and wherein the voltage gap determining circuit provides a voltage gap between the first and second buses of between zero and 1.7 volts.

Claim 5

The computer system as recited in claim 2, wherein the voltage gap determining circuit comprises a voltage divider.

Claim 6

The computer system as recited in claim 1, wherein the voltage control circuit further comprises: a bias circuit which provides a bias voltage to the comparison circuit and the switch.

Claim 7

The computer system as recited in claim 5, wherein bias circuit is coupled to the first bus, and wherein the voltage control circuit further comprises a voltage maintenance circuit which maintains operation of the bias circuit for a predetermined time after a removal of power from the first bus.

Claim 8

The computer system as recited in claim 1, further comprising another voltage control circuit, which prevents an instantaneous voltage on the first bus from exceeding another instantaneous voltage on the second bus during power removal from the computer system and during a short circuit on the second bus, and which is coupled in parallel to the one voltage control circuit.

Claim 9

The computer system as recited in claim 1, wherein the first bus has a steady state voltage of 3.3 volts and the second bus has a steady state voltage of 5 volts.

Claim 10

The computer system as recited in claim 1, wherein the switch comprises: a field effect transistor having a gate, a source, and a drain, wherein the source is connected to a ground, and wherein the drain is connected to the first bus.

Claim 11

The computer system as recited in claim 9, further comprising: a bias circuit which provides a bias voltage to the comparison circuit and a drive voltage to the gate of the field effect transistor.

Claim 12

The computer system as recited in claim 10, wherein the bias circuit comprises: a voltage multiplier for producing the drive voltage, wherein the drive voltage is high enough to drive the field effect transistor into saturation.

Claim 13

The computer system as recited in claim 9, wherein the comparison circuit comprises: a comparator; and a resistance between the comparator and the field effect transistor for limiting capacitive current from the field effect transistor.

Claim 14

The computer system as recited in claim 1, wherein the voltage control circuit further comprises: a voltage maintenance circuit which maintains operation of the voltage control circuit for a predetermined time after the removal of power from the computer system.

Claim 15

A computer system comprising: a circuit element powered by both a first steady state voltage and a second steady state voltage different from the first steady state voltage; a first bus coupled to the circuit element which provides the first steady state voltage; a second bus coupled to the circuit element which provides the second steady state voltage; and a voltage control circuit coupled to the first and second buses which prevents damage to the circuit element by preventing an instantaneous voltage on the first bus from exceeding another instantaneous voltage on the second bus during power removal from the computer system and during a short circuit on the second bus, including a comparison circuit coupled to the first and second buses which compares the instantaneous voltage on the first bus with the instantaneous voltage on the second bus; a switch controlled by the comparison circuit for drawing current from the first bus to reduce the voltage on the first bus to remain below the voltage on the second bus when the voltage on second bus decreases; and a voltage gap determining circuit coupled between the second bus and the comparison circuit which provides a reference voltage to the comparison circuit that is a predetermined fraction of the instantaneous voltage on the second bus.

Claim 16

A computer system comprising: a circuit element powered by both a first steady state voltage and a second steady state voltage different from the first steady state voltage; a first bus coupled to the circuit element which provides the first steady state voltage; a second bus coupled to the circuit element which provides the second steady state voltage; and a voltage control circuit coupled to the first and second buses which prevents damage to the circuit element by preventing an instantaneous voltage on the first bus from exceeding another instantaneous voltage on the second bus during power removal from the computer system and during a short circuit on the second bus, including a comparison circuit coupled to the first and second buses which compares the instantaneous voltage on the first bus with the instantaneous voltage on the second bus; a switch controlled by the comparison circuit for drawing current from the first bus to reduce the voltage on the first bus to remain below the voltage on the second bus when the voltage on second bus decreases; and a voltage gap determining circuit coupled between the second bus and the comparison circuit which provides a reference voltage to the comparison circuit that is a predetermined fraction of the instantaneous voltage on the second bus.

Claim 17

A bus voltage control circuit comprising: a voltage reducing circuit coupled to a first bus and a second bus which prevents damage to a circuit element coupled to the first and second buses by preventing an instantaneous voltage on the first bus from exceeding another instantaneous voltage on the second bus during power removal from the second bus and during a short circuit on the second bus, wherein the voltage reducing circuit includes a comparison circuit coupled to the first and second buses which compares the instantaneous voltage on the first bus with the instantaneous voltage on the second bus, and a switch controlled by the comparison circuit for draw in current from the first bus to reduce the voltage on the first bus to remain below the voltage on the second bus when the voltage on second bus decreases.

Claim 18

A bus voltage control circuit comprising: a voltage reducing circuit coupled to a first bus and a second bus which prevents damage to a circuit element coupled to the first and second buses by preventing an instantaneous voltage on the first bus from exceeding another instantaneous voltage on the second bus during power removal from the second bus and during a short circuit on the second bus, wherein the voltage reducing circuit includes a comparison circuit coupled to the first and second buses which compares the instantaneous voltage on the first bus with the instantaneous voltage on the second bus, and a switch controlled by the comparison circuit for draw in current from the first bus to reduce the voltage on the first bus to remain below the voltage on the second bus when the voltage on second bus decreases.

Claim 19

The bus voltage control circuit as recited in claim 15, wherein the voltage reducing circuit further comprises: a voltage gap determining circuit coupled between the second bus and the comparison circuit which provides a reference voltage to the comparison circuit that is a predetermined fraction of the instantaneous voltage on the second bus.

Claim 20

The bus voltage control circuit as recited in claim 16, wherein the voltage gap determining circuit comprises a voltage divider.

Claim 21

The bus voltage control circuit as recited in claim 15, wherein the voltage reducing circuit further comprises: a bias circuit which provides a bias voltage to the comparison circuit and the switch.

Claim 22

The bus voltage control circuit as recited in claim 15, further comprising another voltage reducing circuit, which prevents an instantaneous voltage on the first bus from exceeding another instantaneous voltage on the second bus during power removal from the second bus and during a short circuit on the second bus, and which is coupled in parallel to the one voltage reducing circuit.

Claim 23

The bus voltage control circuit as recited in claim 15, wherein the first bus has a steady state voltage of 3.3 volts and the second bus has a steady state voltage of 5 volts.

Claim 24

The bus voltage control circuit as recited in claim 15, wherein the switch comprises: a field effect transistor having a gate, a source, and a drain, wherein the source is connected to a ground, and wherein the drain is connected to the first bus.

Claim 25

The bus voltage control circuit as recited in claim 21, wherein the voltage reducing circuit further comprises: a bias circuit which provides a bias voltage to the comparison circuit and a drive voltage to the gate of the field effect transistor.

Claim 26

The bus voltage control circuit as recited in claim 22, wherein the bias circuit comprises: a voltage multiplier for producing the drive voltage, wherein the drive voltage is high enough to drive the field effect transistor into saturation.

Claim 27

The bus voltage control circuit as recited in claim 22, wherein bias circuit is coupled to the first bus, and wherein the bus voltage control circuit further comprises a voltage maintenance circuit which maintains operation of the bias circuit for a predetermined time after a removal of power from the first bus.

Claim 28

The bus voltage control circuit as recited in claim 21, wherein the comparison circuit comprises: a comparator; and a resistance between the comparator and the field effect transistor for limiting capacitive current from the field effect transistor.

Claim 29

The bus voltage control circuit as recited in claim 15, wherein the voltage gap determining circuit provides a voltage gap between the first and second buses of between zero and 1.7 volts.

Claim 30

The bus voltage control circuit as recited in claim 15, wherein the bus voltage control circuit further comprises: a voltage maintenance circuit which maintains operation of the voltage reducing circuit for a predetermined time after the removal of power.

Claim 31

A bus voltage control circuit comprising: a voltage reducing circuit coupled to a first bus and a second bus, which prevents damage to a circuit element coupled to the first and second buses by preventing an instantaneous voltage on the first bus from exceeding another instantaneous voltage on the second bus during power removal from the second bus and during a short circuit on the second bus, and which includes a comparison circuit coupled to the first and second buses which compares the instantaneous voltage on the first bus with the instantaneous voltage on the second bus; a switch controlled by the comparison circuit for drawing current from the first bus to reduce the voltage on the first bus to remain below the voltage on the second bus when the voltage on second bus decreases; and a voltage gap determining circuit coupled between the second bus and the comparison circuit which provides a reference voltage to the comparison circuit that is a predetermined fraction of the instantaneous voltage on the second bus.

Claim 32

A bus voltage control circuit comprising: a voltage reducing circuit coupled to a first bus and a second bus, which prevents damage to a circuit element coupled to the first and second buses by preventing an instantaneous voltage on the first bus from exceeding another instantaneous voltage on the second bus during power removal from the second bus and during a short circuit on the second bus, and which includes a comparison circuit coupled to the first and second buses which compares the instantaneous voltage on the first bus with the instantaneous voltage on the second bus; a switch controlled by the comparison circuit for drawing current from the first bus to reduce the voltage on the first bus to remain below the voltage on the second bus when the voltage on second bus decreases; and a voltage gap determining circuit coupled between the second bus and the comparison circuit which provides a reference voltage to the comparison circuit that is a predetermined fraction of the instantaneous voltage on the second bus.

Claim 35

The method as recited in claim 29, wherein substep (b-1-B) comprises the substep of: (b-1-B-1) keeping the switch closed for a predetermined time after a removal of power on the first bus by the comparison circuit.