US5469082A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peripheral component interfacing system with bus voltage/logic supply comparison means
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1994-12-08
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Granted: 1995-11-21
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Expires: 2014-12-08
Abstract
Abstract Voltage levels of an external bus are sampled with results stored to adjust both an output driver and input receiver. The resulting logic signal levels for the input/output (I/O) interface are maintained within acceptable ranges of the standard I/O signal levels.
Inventors
- 👤 Philip W. Bullinger
- 👤 Michael J. McManus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:00
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/018592
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
116 words
Apparatus for adjusting the voltage levels of logic signals present at a circuit node intended to function as an input and output interface for logic circuitry, comprising: a voltage sense circuit responsive to an enabling signal for comparing a bus supply voltage and a logic circuit supply voltage, and for producing a first output signal as a result of that comparison; an output driver logic circuit responsive to said first output signal for introducing a voltage level to said circuit node corresponding to a logic output voltage level; and a receiver logic circuit responsive to said first output signal for driving said logic circuitry with a voltage having a level corresponding to said first output signal.
Claim 2
Dependent Claim
116 words
Apparatus for adjusting the voltage levels of logic signals present at a circuit node intended to function as an input and output interface for logic circuitry, comprising: a voltage sense circuit responsive to an enabling signal for comparing a bus supply voltage and a logic circuit supply voltage, and for producing a first output signal as a result of that comparison; an output driver logic circuit responsive to said first output signal for introducing a voltage level to said circuit node corresponding to a logic output voltage level; and a receiver logic circuit responsive to said first output signal for driving said logic circuitry with a voltage having a level corresponding to said first output signal.
Claim 3
Dependent Claim
25 words
Apparatus in accordance with claim 1 wherein said voltage sense circuit includes means for maintaining said first output signal whenever said enabling signal is absent.
Claim 4
Dependent Claim
16 words
Apparatus in accordance with claim 2 wherein said means for maintaining is a keeper cell circuit.
Claim 5
Dependent Claim
57 words
Apparatus in accordance with claim 1 wherein said output driver circuit is further responsive to output data and an enabling signal, both of which are produced by the logic circuitry, for generating a signal having the logic value of said output data at the circuit node with the voltage level thereof established by said first output signal.
Claim 6
Dependent Claim
52 words
Apparatus in accordance with claim 4 further comprising a plurality of transistors connected for respectively responding to said first output signal, said output data and said enabling signal; said apparatus further including means for powering said transistors by said interface bus supply voltage for tracking variations of said interface bus supply voltage.
Claim 7
Dependent Claim
38 words
Apparatus in accordance with claim 1 wherein said receiver logic circuit includes an input signal threshold detection circuit responsive to said first output signal for determining whether voltage levels present at the circuit mode are valid logic signals.
Claim 8
Dependent Claim
45 words
Apparatus in accordance with claim 6 wherein said input receiver logic circuit further includes a voltage level shifter circuit responsive to the output of said threshold detection circuit for producing an output signal into the logic circuitry which matches the corresponding logic signal level thereof.
Claim 9
Dependent Claim
35 words
Apparatus in accordance with claim 7 wherein said receiver logic circuit is comprised of a network of transistors at least a portion of which are coupled for receiving power from said interface bus supply voltage.
Claim 10
Independent Claim
63 words
A method of interfacing logic signals into and out of logic circuitry through a common I/O pad connection, comprising the steps of: comparing a bus voltage and a logic circuitry supply voltage for generating a voltage sense control signal; and responding to said voltage sense control signal for driving said I/O pad with logical data having signal levels corresponding to said bus voltage.
Claim 11
Independent Claim
63 words
A method of interfacing logic signals into and out of logic circuitry through a common I/O pad connection, comprising the steps of: comparing a bus voltage and a logic circuitry supply voltage for generating a voltage sense control signal; and responding to said voltage sense control signal for driving said I/O pad with logical data having signal levels corresponding to said bus voltage.
Claim 12
Dependent Claim
54 words
The method of claim 9 further comprising the steps of: detecting whether signals at said pad are at an appropriate level for correlating to a threshold of either a high logic level or a low logic level; and shifting the signals from said detecting step for matching the logic signal levels of said chip.
Claim 13
Dependent Claim
25 words
The method in accordance with claim 9 further comprising the step of tracking variations of said bus voltage while performing said comparing and responding steps.
Claim 14
Dependent Claim
23 words
The method in accordance with claim 10 which includes the step of tracking variations of said bus voltage while performing said detecting steps.
Claim 15
Dependent Claim
25 words
The method in accordance with claim 9 wherein said I/O pad is driven by a pad output driver that is powered by said bus voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |