Clamping circuit for preventing output driving transistor from deep saturation state

Claim 2

A semiconductor integrated circuit comprising: a first power source; a second power source; an input terminal; an output terminal; an input switch having a current path, one end of which is connected to said first power source, and a control end which is connected to said input terminal; an output switch having a current path and a control end, one end of the current path of said output switch being connected to said second power source; first resistor means having a current path including a resistor element, one end of the current path of said first resistor means being connected to the other end of the current path of said input switch; second resistor means having a current path including a resistor element; first wiring means for connecting the other end of the current path of said first resistor means and one end of the current path of said second resistor means, said first wiring means including a first node; second wiring means for connecting the other end of the current path of said second resistor means and the control end of said output switch, said second wiring means including a second node; third wiring means for connecting the other end of the current path of said output switch and said output terminal, said third wiring means including a third node; and comparing means for comparing a first potential difference between said first and second nodes with a second potential difference between said second and third nodes, and for permitting a current to flow from said second node to said third node when said first potential difference is greater than or equal to said second potential difference.

Claim 3

An integrated circuit according to claim 1, wherein said comparing means includes a bipolar transistor having a base connected to said first node, a collector connected to said second node and an emitter connected to said third node.

Claim 4

An integrated circuit according to claim 2, wherein said output switch includes a bipolar transistor having a base connected to the other end of the current path of said second resistor means and a collector connected to said output terminal.

Claim 5

An integrated circuit according to claim 1, wherein said comparing means includes a first bipolar transistor having a base connected to said first node and a collector connected to said second node; and a second bipolar transistor having a base connected to an emitter of said first bipolar transistor, a collector connected to the collector of said first bipolar transistor and an emitter connected to said third node.

Claim 6

A semiconductor integrated circuit comprising: a first power source; a second power source; an input terminal; an output terminal; an input switch having a current path, one end of which is connected to said first power source, and a control end which is connected to said input terminal; a first output switch having a current path and a control end, one end of the current path of said first output switch being connected to said second power source; a second output switch having a current path and a control end, one end of the current path of said second output switch being connected to the control end of said first output switch; first resistor means having a current path including a resistor element, one end of the current path of said first resistor means being connected to the other end of the current path of said input switch; second resistor means having a current path including a resistor element; first wiring means for connecting the other end of the current path of said first resistor means and one end of the current path of said second resistor means, and first wiring means including a first node; second wiring means for connecting the other end of the current path of said second resistor means and the control end of said second output switch, said second wiring means including a second node; third wiring means for connecting the other end of the current path of said first output switch and said output terminal, said third wiring means including a third node; current limiting means for limiting a current, said current limiting means having a current path, one end of which is connected to said first power source and the other end of which is connected to the other end of the current path of said second output switch; and comparing means for comparing a first potential difference between said first and second nodes with a second potential difference between said second and third nodes, and for permitting a current to flow from said second node to said third node when said first potential difference is greater than or equal to said second potential difference.

Claim 7

A semiconductor integrated circuit comprising: a first power source; a second power source; an input terminal; an output terminal; an input switch having a current path, one end of which is connected to said first power source, and a control end which is connected to said input terminal; a first output switch having a current path and a control end, one end of the current path of said first output switch being connected to said second power source; a second output switch having a current path and a control end, one end of the current path of said second output switch being connected to the control end of said first output switch; first resistor means having a current path including a resistor element, one end of the current path of said first resistor means being connected to the other end of the current path of said input switch; second resistor means having a current path including a resistor element; first wiring means for connecting the other end of the current path of said first resistor means and one end of the current path of said second resistor means, and first wiring means including a first node; second wiring means for connecting the other end of the current path of said second resistor means and the control end of said second output switch, said second wiring means including a second node; third wiring means for connecting the other end of the current path of said first output switch and said output terminal, said third wiring means including a third node; current limiting means for limiting a current, said current limiting means having a current path, one end of which is connected to said first power source and the other end of which is connected to the other end of the current path of said second output switch; and comparing means for comparing a first potential difference between said first and second nodes with a second potential difference between said second and third nodes, and for permitting a current to flow from said second node to said third node when said first potential difference is greater than or equal to said second potential difference.

Claim 8

An integrated circuit according to claim 1, wherein said resistor means is a passive element.

Claim 9

A semiconductor integrated circuit comprising: a first power source; a second power source; an input terminal; an output terminal; an input switch having a current path, one end of which is connected to said first power source, and a control end which is connected to said input terminal; a first output switch having a current path and a control end, one end of the current path of said first output switch being connected to said second power source; a second output switch having a current path and a control end, one end of the current path of said second output switch being connected to the control end of said first output switch; first resistor means having a current path including a resistor element, one end of the current path of said first resistor means being connected to the other end of the current path of said input switch; second resistor means having a current path including a resistor element; first wiring means for connecting the other end of the current path of said first resistor means and one end of the current path of said second resistor means, and first wiring means including a first node; second wiring means for connecting the other end of the current path of said second resistor means and the control end of said second output switch, said second wiring means including a second node; third wiring means for connecting the other end of said first output switch and said output terminal, said third wiring means including a third node; current limiting means for limiting a current, said current limiting means having a current path, one end of which is connected to said first power source and the other end of which is connected to the other end of the current path of said second output switch; comparing means for comparing a first potential difference between said first and second nodes with a second potential difference between said second and third nodes, and for permitting a current to flow from said second node to said third node when said first potential difference is greater than or equal to said second potential difference, said comparing means having a first terminal, a second terminal, and a third terminal, said first terminal being connected to said first node, and said second terminal being connected to said second node; and rectifier means including a current path having a first end connected to said third terminal and a second end connected to said third node, said rectifier means allowing a current to flow from said first end to said second end.

Claim 10

A semiconductor integrated circuit comprising: a first power source; a second power source; an input terminal; an output terminal; an input switch having a current path, one end of which is connected to said first power source, and a control end which is connected to said input terminal; a first output switch having a current path and a control end, one end of the current path of said first output switch being connected to said second power source; a second output switch having a current path and a control end, one end of the current path of said second output switch being connected to the control end of said first output switch; first resistor means having a current path including a resistor element, one end of the current path of said first resistor means being connected to the other end of the current path of said input switch; second resistor means having a current path including a resistor element; first wiring means for connecting the other end of the current path of said first resistor means and one end of the current path of said second resistor means, and first wiring means including a first node; second wiring means for connecting the other end of the current path of said second resistor means and the control end of said second output switch, said second wiring means including a second node; third wiring means for connecting the other end of said first output switch and said output terminal, said third wiring means including a third node; current limiting means for limiting a current, said current limiting means having a current path, one end of which is connected to said first power source and the other end of which is connected to the other end of the current path of said second output switch; comparing means for comparing a first potential difference between said first and second nodes with a second potential difference between said second and third nodes, and for permitting a current to flow from said second node to said third node when said first potential difference is greater than or equal to said second potential difference, said comparing means having a first terminal, a second terminal, and a third terminal, said first terminal being connected to said first node, and said second terminal being connected to said second node; and rectifier means including a current path having a first end connected to said third terminal and a second end connected to said third node, said rectifier means allowing a current to flow from said first end to said second end.

Claim 11

An integrated circuit according to claim 1, further comprising: an additional input switch having a current path and a control end, the control end of said additional input switch being connected to said input terminal, one end of the current path of said additional input switch being connected to said second power source, the other end of the current path of said additional input switch being connected to said second node, and said additional input switch being set in the OFF state when said input switch is set in the ON state, and being set in the ON state when said input switch is set in the OFF state.

Claim 12

An integrated circuit according to claim 8, wherein said input switch includes a P-channel insulated gate type FET and said additional input switch includes an N-channel insulated gate type FET.

Claim 13

An integrated circuit according to claim 8, wherein said input switch includes an NPN transistor supplied with an inverted signal of the control signal at the control end thereof and said additional input switch includes an N-channel insulated gate type FET.

Claim 14

A semiconductor integrated circuit comprising: a first power source; a second power source; an input terminal; an output terminal; a first switch having a current path, one end of which is connected to said first power source, and a control end which is connected to said input terminal; a second switch having a current path and a control end, one end of the current path of said first output switch being connected to said second power source; first resistor means having a current path including a resistor element, one end of the current path of said first resistor means being connected to the other end of the current path of said first switch; second resistor means having a current path including a resistor element; first wiring means for connecting the other end of the current path of said first resistor means and one end of the current path of said second resistor means, and first wiring means including a first node; second wiring means for connecting the other end of the current path of said second resistor means and the control end of said second output switch, said second wiring means including a second node; third wiring means for connecting the other end of the current path of said second switch and said output terminal, said third wiring means including a third node; comparing means for comparing a first potential difference between said first and second nodes with a second potential difference between said second and third nodes, and for permitting a current to flow from said second node to said third node when said first potential difference is greater than or equal to said second potential difference, said comparing means having a first terminal, a second terminal, and a third terminal, said first terminal being connected to said first node, and said second terminal being connected to said second node; rectifier means including a current path having a first end connected to said third terminal and a second end connected to said second node, said rectifier means allowing a current to flow from said first end to said second end; and a third switch having a current path and a control end, one end of the current path of said third switch being connected to said third node, the other end of the current path of said third switch being connected to a connection node between said third terminal and said first end of the current path of said rectifier means, and the control end of said third switch being supplied with a control signal.

Claim 15

A semiconductor integrated circuit comprising: a first power source; a second power source; an input terminal; an output terminal; a first switch having a current path, one end of which is connected to said first power source, and a control end which is connected to said input terminal; a second switch having a current path and a control end, one end of the current path of said first output switch being connected to said second power source; first resistor means having a current path including a resistor element, one end of the current path of said first resistor means being connected to the other end of the current path of said first switch; second resistor means having a current path including a resistor element; first wiring means for connecting the other end of the current path of said first resistor means and one end of the current path of said second resistor means, and first wiring means including a first node; second wiring means for connecting the other end of the current path of said second resistor means and the control end of said second output switch, said second wiring means including a second node; third wiring means for connecting the other end of the current path of said second switch and said output terminal, said third wiring means including a third node; comparing means for comparing a first potential difference between said first and second nodes with a second potential difference between said second and third nodes, and for permitting a current to flow from said second node to said third node when said first potential difference is greater than or equal to said second potential difference, said comparing means having a first terminal, a second terminal, and a third terminal, said first terminal being connected to said first node, and said second terminal being connected to said second node; rectifier means including a current path having a first end connected to said third terminal and a second end connected to said second node, said rectifier means allowing a current to flow from said first end to said second end; and a third switch having a current path and a control end, one end of the current path of said third switch being connected to said third node, the other end of the current path of said third switch being connected to a connection node between said third terminal and said first end of the current path of said rectifier means, and the control end of said third switch being supplied with a control signal.

Claim 16

An integrated circuit according to claim 5, wherein said comparing means includes a bipolar transistor having a base connected to said first node, a collector connected to said second node and an emitter connected to said third node.

Claim 17

An integrated circuit according to claim 5, wherein said first output switch includes a first bipolar transistor having an emitter connected to said second power source and a collector connected to said third node; and said second output switch includes a second bipolar transistor having a base connected to said second node, an emitter connected to the base of said first bipolar transistor, and a collector connected to the other end of the current path of said current limiting means.

Claim 18

An integrated circuit according to claim 5, wherein said comparing means includes a first bipolar transistor having a base connected to said first node and a collector connected to said second node; and a second bipolar transistor having a base connected to an emitter of said first bipolar transistor, a collector connected to the collector of said first bipolar transistor and an emitter connected to said third node.

Claim 19

An integrated circuit according to claim 5, wherein said current limiting means is a resistor.

Claim 20

An integrated circuit according to claim 5, wherein said first and second resistor means are passive elements.

Claim 21

An integrated circuit according to claim 15, wherein said resistor is a passive element.

Claim 22

An integrated circuit according to claim 5, further comprising: a first additional input switch having a current path and a control end, the control end of said first additional input switch being connected to said input terminal, one end of the current path of said first additional input switch being connected to said second power source, the other end of the current path of said first additional input switch being connected to said second node, and said first additional input switch being set in the OFF state when said input switch is set in the ON state, and being set in the ON state when said input switch is set in the OFF state; and a second additional input switch having a current path and a control end, the control end of said second additional input switch being connected to said input terminal, one end of the current path of said second additional input switch being connected to said second power source, the other end of the current path of said second additional input switch being connected to a connection node between the control end of said first output switch and one end of the current path of said second output switch, and said second additional input switch being set in the OFF state when said input switch is set in the ON state, and being set in the ON state when said input switch is set in the OFF state.

Claim 23

An integrated circuit according to claim 18, wherein said input switch includes a P-channel insulated gate type FET, said first additional input switch includes an N-channel insulated gate type FET, and said second additional input switch includes an N-channel insulated gate type FET.

Claim 24

An integrated circuit according to claim 19, wherein said input switch includes an NPN transistor supplied with the inverted form of said control signal at the control end thereof, said first additional input switch includes an N-channel insulated gate type FET, and said second additional input switch includes an N-channel insulated gate type FET.

Claim 25

An integrated circuit according to claim 5, further comprising: a first additional input switch having a current path and a control end, the control end of said first additional input switch being connected to said input terminal, one end of the current path of said first additional input switch being connected to said second power source, the other end of the current path of said first additional input switch being connected to said second node, and said first additional input switch being set in the OFF state when said input switch is set in the ON state, and being set in the ON state when said input switch is set in the OFF state; a second additional input switch having a current path and a control end, the control end of said second additional input switch being connected to said input terminal, one end of the current path of said second additional input switch being connected to said second power source, the other end of the current path of said second additional input switch being connected to a connection node between the control end of said first output switch and one end of the current path of said second output switch, and said second additional input switch being set in the OFF state when said input switch is set in the ON state, and being set in the ON state when said input switch is set in the OFF state; and a further input terminal; and a third additional input switch having a current path and a control end, the control end of said third additional input switch being connected to said further input terminal, one end of the current path of said third additional input switch being connected to said first power source, and the other end of the current path of, and said third additional input switch being connected to said third node.

Claim 26

An integrated circuit according to claim 5, wherein an amount of current flowing in the current path of said second output switch is controlled to change an output voltage of said first output switch which receives the current therefrom at the control end by changing an amount of current supplied from said current limiting means.

Claim 27

An integrated circuit according to claim 15, wherein an amount of current flowing in the current path of said second output switch is controlled to change an output voltage of said first output switch which receives the current therefrom at the control end by changing the resistance of said resistor.

Claim 28

A semiconductor integrated circuit comprising: a first power source; a second power source; an input terminal; an output terminal; a first switch having a current path, one end of which is connected to said first power source, and a control end which is connected to said input terminal; a second switch having a current path and a control end, one end of the current path of said first output switch being connected to said second power source; a third switch having a current path and a control end, one end of the current path of said third switch being connected to the control end of said second switch; a first resistor having a current path including a resistor element, one end of the current path of said first resistor being connected to the other end of the current path of said first switch; second resistor means having a current path including a resistor element; first wiring means for connecting the other end of the current path of said first resistor means and one end of the current path of said second resistor, said first wiring means including a first node; second wiring means for connecting the other end of the current path of said second resistor means and the control end of said third switch; third wiring means for connecting the other end of the current path of said second switch and said output terminal, said third wiring means including a second node; current limiting means for limiting a current, said current limiting means having a current path, one end of which is connected to said first power source and the other end of which is connected to the other end of the current path of said third switch; and a rectifier for permitting a current to flow from said first node to said second node when a difference between a first potential of said first node and a second potential of said second node is equal to or less than a predetermined value; wherein output characteristics of said second switch are controlled by adjusting the degree to which the current is limited by said current limiting means.

Claim 29

A semiconductor integrated circuit comprising: a first power source; a second power source; an input terminal; an output terminal; a first switch having a current path, one end of which is connected to said first power source, and a control end which is connected to said input terminal; a second switch having a current path and a control end, one end of the current path of said first output switch being connected to said second power source; a third switch having a current path and a control end, one end of the current path of said third switch being connected to the control end of said second switch; a first resistor having a current path including a resistor element, one end of the current path of said first resistor being connected to the other end of the current path of said first switch; second resistor means having a current path including a resistor element; first wiring means for connecting the other end of the current path of said first resistor means and one end of the current path of said second resistor, said first wiring means including a first node; second wiring means for connecting the other end of the current path of said second resistor means and the control end of said third switch; third wiring means for connecting the other end of the current path of said second switch and said output terminal, said third wiring means including a second node; current limiting means for limiting a current, said current limiting means having a current path, one end of which is connected to said first power source and the other end of which is connected to the other end of the current path of said third switch; and a rectifier for permitting a current to flow from said first node to said second node when a difference between a first potential of said first node and a second potential of said second node is equal to or less than a predetermined value; wherein output characteristics of said second switch are controlled by adjusting the degree to which the current is limited by said current limiting means.

Claim 30

An integrated circuit according to claim 7, wherein said rectifier means is a bipolar transistor whose collector and base are commonly connected to said third terminal and whose emitter is connected to said third node.

Claim 31

An integrated circuit according to claim 7, wherein said rectifier means is a bipolar transistor whose collector and base are commonly connected to said third node and whose emitter is connected to said output terminal.

Claim 32

An integrated circuit according to claim 11, wherein said third switch is an insulated gate type FET having one of the source and drain as said one end, the other of said source and drain as said other end and a gate as said control end.

Claim 33

An integrated circuit according to claim 11, wherein said rectifier means is a diode having an anode connected to said third terminal and a cathode connected to said second node.

Claim 34

An integrated circuit according to claim 11, wherein said rectifier means is a bipolar transistor whose collector and base are commonly connected to said third terminal and whose emitter is connected to said second node.

Claim 35

An integrated circuit according to claim 11, wherein said comparing means is bipolar transistor having a base connected to said first node, a collector connected to said second node, and an emitter connected to said third node.

Claim 36

An integrated circuit according to claim 30, wherein said second switch is a bipolar transistor having a base connected to said second node and a collector connected to said third node, and an emitter connected to said second power source.

Claim 37

An integrated circuit according to claim 11, wherein said first and second resistor means are passive elements.

Claim 38

An integrated circuit according to claim 11, further comprising: a fourth switch having a current path and a control end, the control end of said fourth switch being connected to said input terminal, one end of the current path of said fourth switch being connected to said second power source, the other end of the current path of said fourth switch being connected to said second node, and said fourth switch being set in the OFF state when said first switch is set in the ON state, and being set in the ON state when said first switch is set in the OFF state.

Claim 39

An integrated circuit according to claim 33, wherein the control end of said third switch is connected to a connection node between one end of the current path of said first resistor means and the other end of the current path of said first switch, and receives the control signal from said other end of the current path of said first switch.

Claim 40

An integrated circuit according to claim 34, wherein said first switch is a P-channel insulated gate type FET and said fourth switch is an N-channel insulated gate type FET.

Claim 41

An integrated circuit according to claim 6, wherein said passive elements are of the same type.

Claim 42

An integrated circuit according to claim 16, wherein said passive elements are of the same type.

Claim 43

An integrated circuit according to claim 7, wherein said first and second resistor means are passive elements of the same type.

Claim 44

An integrated circuit according to claim 32, wherein said passive elements are of the same type.