US3676713A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Saturation control scheme for ttl circuit
Assignee: International Business Machines Corp
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Filing: 1971-04-23
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Granted: 1972-07-11
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Expires: 1991-04-23
Abstract
Abstract This specification discloses a technique of saturation control for a transistor transistor logic (TTL) circuit which is also applicable to other types of circuits. The saturation control device is a transistor whose emitter is connected to the collector of the output transistor of the TTL circuit, its collector is connected to the base of the output transistor for the TTL circuit and its base is connected through a resistive divider network between the base and collector of the input transistor for the TTL circuit. This saturation control transistor is formed in the same isolation pocket with the input transistor for the TTL circuit by providing the input transistor with an extended base region and an additional emitter diffusion which is spaced from the other emitter diffusions and the collector contact for the input transistor so that the sections of the extended base region between the additional emitter diffusion and the other emitter diffusions and between the additional emitter diffusion and the collector contact form the resistors of the divider network.
Inventors
- 👤 Siegfried K Wiedmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088; H03K19/01; H03K19/013
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
274 words
A transistor circuit which does not go into deep saturation comprising: a driver transistor arranged in a common emitter configuration so that the base of the transistor receives drive current and an output is taken off the collector; drive means coupled to the base of the driven transistor for supplying drive current to said base of the driven transistor, said drive means comprising a multi-emitter transistor with a collector connected to the base of the driven transistor, and emitters serving as individual inputs for the circuit, and a current source coupled to the base of the multi-emitter transistor so that said circuit serves as an AND gate; an antisaturation transistor with an emitter coupled to the collector of the driven transistor and a collector coupled to the base of the driven transistor; and a resistive divider network coupled between the base of the multi-emitter transistor and the collector and having a portion thereof coupled between the base and collector of said antisaturation transistor to form a biasing means for biasing the base of the antisaturation transistor at a potential greater than the emitter base voltage of the driven transistor when the driven transistor is conducting, wherein said potential is large enough to prevent the operation of the antisaturation transistor from significantly effecting the turn-on time of the first transistor but small enough to allow the antisaturation transistor to be turned on when the collector of the driven transistor starts to drop as the driven transistor tends to go into saturation whereby the antisaturation transistor conducts and shunts base drive current by the driven transistor and thereby prevents the driven transistor from going into saturation.
Claim 2
Dependent Claim
274 words
A transistor circuit which does not go into deep saturation comprising: a driver transistor arranged in a common emitter configuration so that the base of the transistor receives drive current and an output is taken off the collector; drive means coupled to the base of the driven transistor for supplying drive current to said base of the driven transistor, said drive means comprising a multi-emitter transistor with a collector connected to the base of the driven transistor, and emitters serving as individual inputs for the circuit, and a current source coupled to the base of the multi-emitter transistor so that said circuit serves as an AND gate; an antisaturation transistor with an emitter coupled to the collector of the driven transistor and a collector coupled to the base of the driven transistor; and a resistive divider network coupled between the base of the multi-emitter transistor and the collector and having a portion thereof coupled between the base and collector of said antisaturation transistor to form a biasing means for biasing the base of the antisaturation transistor at a potential greater than the emitter base voltage of the driven transistor when the driven transistor is conducting, wherein said potential is large enough to prevent the operation of the antisaturation transistor from significantly effecting the turn-on time of the first transistor but small enough to allow the antisaturation transistor to be turned on when the collector of the driven transistor starts to drop as the driven transistor tends to go into saturation whereby the antisaturation transistor conducts and shunts base drive current by the driven transistor and thereby prevents the driven transistor from going into saturation.
Claim 3
Dependent Claim
86 words
The circuit of claim 1 wherein said multi-emitter transistor and the antisaturation transistor share common collector and base regions and wherein said base region is elongated, has mounted thereon a base contact for the said multi-emitter and antisaturation transistors, and a contact to the collector of said multi-emitter and antisaturation transistors and contains between the base and collector contacts an emitter diffusion for the antisaturation transistor so that the resistors of the resistive divider network are formed integraLly in the base region of said two transistors.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-11 | 1976-01-10 | 1976-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-11 | 1980-01-10 | 1980-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-11 | 1984-01-10 | 1984-07-11 | $7700.00 | Window Closed / Lapsed |