US5260904A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data bus clamp circuit for a semiconductor memory device
Assignee: Lapis Semiconductor Co Ltd
•
Filing: 1991-11-26
•
Granted: 1993-11-09
•
Expires: 2011-11-26
Abstract
Abstract A data bus clamping circuit for use in a semiconductor memory device includes a memory cell array for storing data, a row address decoder for decoding row address signals taken in by a row address strobe signal to select memory cells in a row direction of the memory cell array, a column address decoder for decoding column address signals based on a column address decoder enabling signal to select memory cells in a column direction of the memory cell array, complementary data buses for transmitting data read out from the memory cell array, a data bus pull-up circuit for pulling up the complementary data buses, and a differential amplification type of readout circuit for amplifying on a differential basis data on the complementary data buses to output readout data. The data bus clamping circuit includes a first discharge circuit for discharging electric charge on the complementary data buses during an active period of the row address strobe signal, and a second discharge circuit for discharging electric charge on the complementary data buses with a discharge ability larger than the first discharge circuit, during a period of time from the time the active period of the row address strobe signal starts until the column address decoder enabling signal becomes active.
Inventors
- 👤 Masahumi Miyawaki
- 👤 Tamihiro Ishimura
- 👤 Yoshio Ohtsuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:13
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1048
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
186 words
A semiconductor memory device comprising: a memory cell array; a row address decoder coupled to said memory cell array through a plurality of word lines, said row address decoder selecting a word line in response to a row address strobe signal; a column address decoder coupled to a data bus and to said memory cell array through a plurality of bit lines, said column address decoder transferring data on the bit lines to the data bus in response to a column address decoder enabling signal; a control circuit for generating a control signal at first and second levels in response to the row address strobe signal and the column address decoder enabling signal, respectively; a first clamping circuit coupled to the data bus for changing a level on the data bus to a third level in response to the control signal; and a second clamping circuit coupled to the data bus for changing the level on the data bus to the third level in response to the control signal, said second clamping circuit having a level changing ability higher than that of said first clamping circuit.
Claim 2
Dependent Claim
186 words
A semiconductor memory device comprising: a memory cell array; a row address decoder coupled to said memory cell array through a plurality of word lines, said row address decoder selecting a word line in response to a row address strobe signal; a column address decoder coupled to a data bus and to said memory cell array through a plurality of bit lines, said column address decoder transferring data on the bit lines to the data bus in response to a column address decoder enabling signal; a control circuit for generating a control signal at first and second levels in response to the row address strobe signal and the column address decoder enabling signal, respectively; a first clamping circuit coupled to the data bus for changing a level on the data bus to a third level in response to the control signal; and a second clamping circuit coupled to the data bus for changing the level on the data bus to the third level in response to the control signal, said second clamping circuit having a level changing ability higher than that of said first clamping circuit.
Claim 3
Dependent Claim
29 words
A device according to claim 1, wherein said first and second clamping circuits change the level on the data bus when the control signal is at the first level.
Claim 4
Dependent Claim
51 words
A device according to claim 2, wherein said control circuit continues to produce the control signal at the first level in response to said row address decoder starting to latch the data until immediately before said column address decoder transfers the second signal on the bit line to the data bus.
Claim 5
Dependent Claim
19 words
A device according to claim 1, wherein the first and second levels re high voltage and ground levels, respectively.
Claim 6
Dependent Claim
14 words
A device according to claim 1, wherein the third level is a ground level.
Claim 7
Dependent Claim
22 words
A device according to claim 1, further comprising a sense amplifier coupled between said memory cell array and said column address decoder.
Claim 8
Dependent Claim
20 words
A device according to claim 1, further comprising a differential amplification type of readout circuit coupled to the data bus.
Claim 9
Dependent Claim
195 words
A semiconductor memory device comprising: a memory cell array having a plurality of pairs of bit lines and a plurality of word lines; a row address decoder coupled to the word lines, said row address decoder selecting a word line in response to a first signal; a column address decoder coupled to the plurality of pairs of bit lines and to a pair of data buses, said column address decoder transferring data on a predetermined pair of the plurality of pairs of bit lines to the pair of data buses in response to a second signal generated from the first signal; a control circuit for generating a control signal at first and second levels in response to the first and second signals, respectively; a first clamping circuit connected to the data buses for changing a level on the data bus to a third level in response to the control signal; and a second clamping circuit coupled to the data buses for changing the level on the data bus to the third level in response to the control signal, said second clamping circuit having a level changing ability higher than that of said first clamping circuit.
Claim 10
Dependent Claim
195 words
A semiconductor memory device comprising: a memory cell array having a plurality of pairs of bit lines and a plurality of word lines; a row address decoder coupled to the word lines, said row address decoder selecting a word line in response to a first signal; a column address decoder coupled to the plurality of pairs of bit lines and to a pair of data buses, said column address decoder transferring data on a predetermined pair of the plurality of pairs of bit lines to the pair of data buses in response to a second signal generated from the first signal; a control circuit for generating a control signal at first and second levels in response to the first and second signals, respectively; a first clamping circuit connected to the data buses for changing a level on the data bus to a third level in response to the control signal; and a second clamping circuit coupled to the data buses for changing the level on the data bus to the third level in response to the control signal, said second clamping circuit having a level changing ability higher than that of said first clamping circuit.
Claim 11
Dependent Claim
29 words
A device according to claim 8, wherein said first and second clamping circuits change the level on the data buses when the control signal is at the first level.
Claim 12
Dependent Claim
48 words
A device according to claim 9, wherein said control circuit produces the control signal in the first level when said row address decoder latches the data and said column address decoder does not transfer the second signal on the predetermined pair of bit lines to the data buses.
Claim 13
Dependent Claim
19 words
A device according to claim 8, wherein the first and second levels are high voltage and ground levels, respectively.
Claim 14
Dependent Claim
14 words
A device according to claim 8, wherein the third level is a ground level.
Claim 15
Dependent Claim
27 words
A device according to claim 8, wherein the first signal is a row address latch signal and the second signal is a column address decoder enabling signal.
Claim 16
Dependent Claim
37 words
A device according to claim 8, further comprising a sense amplifier coupled to bit lines and between said memory cell array and said column address decoder for amplifying difference of levels on the pair of bit lines.
Claim 17
Dependent Claim
31 words
A device according to claim 8, further comprising a differential amplification type of readout circuit coupled to the data bus for amplifying difference of levels on the pair of data buses.
References Cited (Backward Citations)
US4494222A
Cited
EP0178921A2
Cited
EP0184148A2
Cited
US4636986A
Cited
US4636986B1
Cited
US4809230A
Cited
US4985868A
Cited
US4961168A
Cited
US5083296A
Cited
US5091886A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-08 | 1997-05-10 | 1997-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-08 | 2001-05-10 | 2001-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-08 | 2005-05-10 | 2005-11-09 | $7700.00 | Window Closed / Lapsed |