High-frequency phase locked loop circuit

Claim 2

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein the output of the exclusive-OR circuit provides a clock signal.

Claim 3

The circuit as recited in claim 1, wherein the inputs of the first and second phase-locked loop circuits are coupled to a crystal which produces a signal having a predetermined frequency; and wherein the clock signal has an output frequency which is a multiple of the predetermined frequency.

Claim 4

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein the inputs of the first and second phase-locked loop circuits are coupled to a crystal which produces a signal having a predetermined frequency; wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is a multiple of the predetermined frequency; and wherein the circuit comprises CMOS transistors and the output frequency is greater than 500M Hz.

Claim 5

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein the inputs of the first and second phase-locked loop circuits are coupled to a crystal which produces a signal having a predetermined frequency; wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is a multiple of the predetermined frequency; and wherein the circuit comprises CMOS transistors and the output frequency is greater than 500M Hz.

Claim 6

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein the inputs of the first and second phase-locked loop circuits are coupled to a crystal which produces a signal having a predetermined frequency; wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is a multiple of the predetermined frequency; and wherein the circuit comprises CMOS transistors and the output frequency is greater than 1 GHz.

Claim 7

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein the inputs of the first and second phase-locked loop circuits are coupled to a crystal which produces a signal having a predetermined frequency; wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is a multiple of the predetermined frequency; and wherein the circuit comprises CMOS transistors and the output frequency is greater than 1 GHz.

Claim 8

The circuit as recited in claim 1, wherein the first phase-locked loop circuit comprises: a divide-by-N circuit having the input to the first phase-locked loop circuit and an output; a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-N circuit; a charge pump having an input coupled to the output of the phase detector and an output; a loop filter having an input coupled to the output of the charge pump and an output; a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the first input of the exclusive-OR circuit; and a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector.

Claim 9

The circuit as recited in claim 5, wherein the second phase-locked loop circuit comprises: a divide-by-O circuit having the input to the second phase-locked loop circuit and an output; a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-O circuit; a charge pump having an input coupled to the output of the phase detector and an output; a loop filter having an input coupled to the output of the charge pump and an output; a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the second input of the exclusive-OR circuit; and a divide-by-P circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector.

Claim 10

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output; wherein the first phase-locked loop circuit comprises: a divide-by-N circuit having the input to the first phase-locked loop circuit and an output; a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-N circuit; a charge pump having an input coupled to the output of the phase detector and an output; a loop filter having an input coupled to the output of the charge pump and an output; a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the first input of the exclusive-OR circuit; and a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector; and wherein the second phase-locked loop circuit comprises: a divide-by-O circuit having the input to the second phase-locked loop circuit and an output; a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-O circuit; a charge pump having an input coupled to the output of the phase detector and an output; a loop filter having an input coupled to the output of the charge pump and an output; a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the second input of the exclusive-OR circuit; and a divide-by-P circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector; wherein the inputs of the first and second phase-locked loop circuits are coupled to a crystal which produces an input signal having a predetermined input frequency; wherein ratios M:N and P:O are equal to a common ratio; and wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is equal to the input frequency multiplied by twice the common ratio.

Claim 11

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output; wherein the first phase-locked loop circuit comprises: a divide-by-N circuit having the input to the first phase-locked loop circuit and an output; a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-N circuit; a charge pump having an input coupled to the output of the phase detector and an output; a loop filter having an input coupled to the output of the charge pump and an output; a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the first input of the exclusive-OR circuit; and a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector; and wherein the second phase-locked loop circuit comprises: a divide-by-O circuit having the input to the second phase-locked loop circuit and an output; a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-O circuit; a charge pump having an input coupled to the output of the phase detector and an output; a loop filter having an input coupled to the output of the charge pump and an output; a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the second input of the exclusive-OR circuit; and a divide-by-P circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector; wherein the inputs of the first and second phase-locked loop circuits are coupled to a crystal which produces an input signal having a predetermined input frequency; wherein ratios M:N and P:O are equal to a common ratio; and wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is equal to the input frequency multiplied by twice the common ratio.

Claim 12

The circuit as recited in claim 7, wherein the divide-by-N circuit triggers on a positive edge of the input signal from the crystal and the divide-by-O circuit triggers on a negative edge of the input signal from the crystal.

Claim 13

The circuit as recited in claim 8, wherein a first signal at the first input of the exclusive-OR circuit and a second signal at the second input of the exclusive-OR circuit differ in phase by about ninety degrees.

Claim 14

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein the first phase-locked loop circuit comprises: a divide-by-N circuit having the input to the first phase-locked loop circuit and an output; a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-N circuit; a charge pump having an input coupled to the output of the phase detector and an output; a loop filter having an input coupled to the output of the charge pump and an output; a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the first input of the exclusive-OR circuit; and a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector, wherein the first phase-locked loop circuit comprises a master phase-locked loop circuit, and wherein the second phase-locked loop circuit comprises a slave phase-locked loop circuit which is clocked by the master phase-locked loop circuit.

Claim 15

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein the first phase-locked loop circuit comprises: a divide-by-N circuit having the input to the first phase-locked loop circuit and an output; a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-N circuit; a charge pump having an input coupled to the output of the phase detector and an output; a loop filter having an input coupled to the output of the charge pump and an output; a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the first input of the exclusive-OR circuit; and a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector, wherein the first phase-locked loop circuit comprises a master phase-locked loop circuit, and wherein the second phase-locked loop circuit comprises a slave phase-locked loop circuit which is clocked by the master phase-locked loop circuit.

Claim 16

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output; wherein the first phase-locked loop circuit comprises: a divide-by-N circuit having the input to the first phase-locked loop circuit and an output; a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-N circuit; a charge pump having an input coupled to the output of the phase detector and an output; a loop filter having an input coupled to the output of the charge pump and an output; a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the first input of the exclusive-OR circuit; and a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector, wherein the first phase-locked loop circuit comprises a master phase-locked loop circuit, and wherein the second phase-locked loop circuit comprises a slave phase-locked loop circuit which is clocked by the master phase-locked loop circuit; wherein the second phase-locked loop circuit comprises: a divide-by-O circuit having the input to the second phase-locked loop circuit and an output; a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-O circuit; a charge pump having an input coupled to the output of the phase detector and an output; a loop filter having an input coupled to the output of the charge pump and an output; a delay circuit having a first input coupled to the output of the loop filter, a second input coupled to the output of the voltage-controlled oscillator of the first phase-locked loop circuit, and an output coupled to the second input of the exclusive-OR circuit; and a divide-by-P circuit having an input coupled to the output of the delay circuit and an output coupled to the second input of the phase detector.

Claim 17

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output; wherein the first phase-locked loop circuit comprises: a divide-by-N circuit having the input to the first phase-locked loop circuit and an output; a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-N circuit; a charge pump having an input coupled to the output of the phase detector and an output; a loop filter having an input coupled to the output of the charge pump and an output; a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the first input of the exclusive-OR circuit; and a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector, wherein the first phase-locked loop circuit comprises a master phase-locked loop circuit, and wherein the second phase-locked loop circuit comprises a slave phase-locked loop circuit which is clocked by the master phase-locked loop circuit; wherein the second phase-locked loop circuit comprises: a divide-by-O circuit having the input to the second phase-locked loop circuit and an output; a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-O circuit; a charge pump having an input coupled to the output of the phase detector and an output; a loop filter having an input coupled to the output of the charge pump and an output; a delay circuit having a first input coupled to the output of the loop filter, a second input coupled to the output of the voltage-controlled oscillator of the first phase-locked loop circuit, and an output coupled to the second input of the exclusive-OR circuit; and a divide-by-P circuit having an input coupled to the output of the delay circuit and an output coupled to the second input of the phase detector.

Claim 18

The circuit as recited in claim 11, wherein the inputs of the first and second phase-locked loop circuits are coupled to a crystal which produces an input signal having a predetermined input frequency; wherein ratios M:N and P:O are equal to a common ratio; and wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is equal to the input frequency multiplied by twice the common ratio.

Claim 19

The circuit as recited in claim 12, wherein the divide-by-N circuit triggers on a positive edge of the input signal from the crystal and the divide-by-O circuit triggers on a negative edge of the input signal from the crystal.

Claim 20

The circuit as recited in claim 13, wherein a first signal at the first input of the exclusive-OR circuit and a second signal at the second input of the exclusive-OR circuit differ in phase by about ninety degrees.

Claim 21

A CMOS phase-locked loop circuit comprising: a first phase-locked loop sub-circuit having an input and an output, including a divide-by-N circuit having the input to the first phase-locked loop sub-circuit and an output; and a first circuit including a phase detector having a first input coupled to the output of the divide-by-N circuit, and a second input; and a divide-by-M circuit having an input coupled to the output of the first phase-locked loop sub-circuit, and an output coupled to the second input of the phase detector; a second phase-locked loop sub-circuit having an input coupled to the input of the first phase-locked loop sub-circuit and an output, including a divide-by-N circuit having the input to the second phase-locked loop sub-circuit and an output; and a second circuit including a phase detector having a first input coupled to the output of the divide-by-N circuit, and a second input; and a divide-by-M circuit having an input coupled to the output of the second phase-locked loop sub-circuit, and an output coupled to the second input of the phase detector; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop sub-circuits and an output; wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is equal to an input frequency of an input signal applied to the inputs of the first and second phase-locked loop sub-circuits multiplied by twice the ratio M:N.

Claim 22

A CMOS phase-locked loop circuit comprising: a first phase-locked loop sub-circuit having an input and an output, including a divide-by-N circuit having the input to the first phase-locked loop sub-circuit and an output; and a first circuit including a phase detector having a first input coupled to the output of the divide-by-N circuit, and a second input; and a divide-by-M circuit having an input coupled to the output of the first phase-locked loop sub-circuit, and an output coupled to the second input of the phase detector; a second phase-locked loop sub-circuit having an input coupled to the input of the first phase-locked loop sub-circuit and an output, including a divide-by-N circuit having the input to the second phase-locked loop sub-circuit and an output; and a second circuit including a phase detector having a first input coupled to the output of the divide-by-N circuit, and a second input; and a divide-by-M circuit having an input coupled to the output of the second phase-locked loop sub-circuit, and an output coupled to the second input of the phase detector; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop sub-circuits and an output; wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is equal to an input frequency of an input signal applied to the inputs of the first and second phase-locked loop sub-circuits multiplied by twice the ratio M:N.

Claim 23

A CMOS circuit comprising: a master phase-locked loop sub-circuit having an input and an output, including a divide-by-N circuit having the input to the master phase-locked loop sub-circuit and an output; and a first circuit including a phase detector having a first input coupled to the output of the divide-by-N circuit, and a second input; a voltage-controlled oscillator having an output coupled to the output of the master phase-locked loop sub-circuit; and a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector; a slave phase-locked loop sub-circuit having an input coupled to the input of the master phase-locked loop sub-circuit and an output, including a divide-by-N circuit having the input to the slave phase-locked loop sub-circuit and an output; and a second circuit including a phase detector having a master input coupled to the output of the divide-by-N circuit, and a second input; a delay circuit having an input coupled to the output of the voltage-controlled oscillator of the master phase-locked loop sub-circuit, and an output coupled to the output of the slave phase-locked loop sub-circuit; and a divide-by-M circuit having an input coupled to the output of the delay circuit and an output coupled to the second input of the phase detector; and an exclusive-OR circuit having master and second inputs coupled to the outputs of the master and slave phase-locked loop sub-circuits and an output; wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is equal to an input frequency of an input signal applied to the inputs of the master and slave phase-locked loop sub-circuits multiplied by twice the ratio M:N.

Claim 24

A CMOS circuit comprising: a master phase-locked loop sub-circuit having an input and an output, including a divide-by-N circuit having the input to the master phase-locked loop sub-circuit and an output; and a first circuit including a phase detector having a first input coupled to the output of the divide-by-N circuit, and a second input; a voltage-controlled oscillator having an output coupled to the output of the master phase-locked loop sub-circuit; and a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector; a slave phase-locked loop sub-circuit having an input coupled to the input of the master phase-locked loop sub-circuit and an output, including a divide-by-N circuit having the input to the slave phase-locked loop sub-circuit and an output; and a second circuit including a phase detector having a master input coupled to the output of the divide-by-N circuit, and a second input; a delay circuit having an input coupled to the output of the voltage-controlled oscillator of the master phase-locked loop sub-circuit, and an output coupled to the output of the slave phase-locked loop sub-circuit; and a divide-by-M circuit having an input coupled to the output of the delay circuit and an output coupled to the second input of the phase detector; and an exclusive-OR circuit having master and second inputs coupled to the outputs of the master and slave phase-locked loop sub-circuits and an output; wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is equal to an input frequency of an input signal applied to the inputs of the master and slave phase-locked loop sub-circuits multiplied by twice the ratio M:N.

Claim 29

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein a first signal at the first input of the exclusive-OR circuit and a second signal at the second input of the exclusive-OR circuit differ in phase by about ninety degrees.

Claim 30

A circuit comprising: a first phase-locked loop circuit having an input and an output; a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output; and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein a first signal at the first input of the exclusive-OR circuit and a second signal at the second input of the exclusive-OR circuit differ in phase by about ninety degrees.

Claim 31

The circuit as recited in claim 1, wherein the clock signal has a frequency greater than signal frequency at the first input of the exclusive-OR circuit.

Claim 32

The circuit as recited in claim 1, wherein the clock signal has a frequency greater than signal frequency at the first and second inputs of the exclusive-0R circuit.

Claim 33

The circuit as recited in claim 1, wherein the first phase-locked loop circuit comprises a master phase-locked loop circuit, and wherein the second phase-locked loop circuit comprises a slave phase-locked loop circuit which is clocked by the master phase-locked loop circuit.

Claim 34

The circuit as recited in claim 17, wherein a first signal at the first input of the exclusive-OR circuit and a second signal at the second input of the exclusive-0R circuit differ in phase by about ninety degrees.