US4814727A
Expired / Lapsed
US
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Wide-deviation tracking filter circuit
Assignee: Unisys Corp
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Filing: 1987-12-18
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Granted: 1989-03-21
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Expires: 2007-12-18
Abstract
Abstract A wide deviation tracking filter is provided which has the input signal to be tracked applied to a low frequency phase-locked loop circuit which performs coarse filtering of the phase noise on the input signal. A digital phase shifter is connected in series in the low frequency phase-locked loop and produces a pair of quadrature clock signals which are at the frequency of the input signal and at half the frequency of the output of the voltage control oscillator of the low frequency phase-locked loop. The pair of quadrature signals are connected to an image reject circuit. The image reject circuit is connected in series in the loop of a high frequency phase-locked loop which operates at a much higher frequency than the low frequency phase-locked loop and performs the function of further filtering the phase noise on the input signal to provide an output signal having ultra-low phase noise.
Inventors
- 👤 Vaughn L. Mower
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:36
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/07
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
201 words
A wide deviation tracking filter, comprising: input signal means having at least one stable well defined waveform edge, a low frequency phase-locked loop coupled to said input signal means having a voltage controlled oscillator which is driven at twice the input signal frequency, said input signal means having a bandwidth greater than two, a wide frequency range digital phase shifter coupled to said low frequency phase-locked loop for producing a pair of quadrature clock signals at the input signal frequency, a high frequency phase-locked loop having a high frequency stable oscillator input and an ultra-low phase noise signal output having the same phase and frequency as the input signal, image rejection means connected in series in said high frequency phase-locked loop at the output of the loop voltage controlled oscillator, said image rejection means having a pair of mixers coupled to said quadrature clock signals from said digital phase shifter and a quadrature hybrid circuit coupled to the output of said mixers for producing a noisy replica of said stable oscillator input signal that is applied to the phase detector of the high frequency phase-locked loop for producing a tracking error signal which is applied to said loop voltage controlled oscillator.
Claim 2
Dependent Claim
201 words
A wide deviation tracking filter, comprising: input signal means having at least one stable well defined waveform edge, a low frequency phase-locked loop coupled to said input signal means having a voltage controlled oscillator which is driven at twice the input signal frequency, said input signal means having a bandwidth greater than two, a wide frequency range digital phase shifter coupled to said low frequency phase-locked loop for producing a pair of quadrature clock signals at the input signal frequency, a high frequency phase-locked loop having a high frequency stable oscillator input and an ultra-low phase noise signal output having the same phase and frequency as the input signal, image rejection means connected in series in said high frequency phase-locked loop at the output of the loop voltage controlled oscillator, said image rejection means having a pair of mixers coupled to said quadrature clock signals from said digital phase shifter and a quadrature hybrid circuit coupled to the output of said mixers for producing a noisy replica of said stable oscillator input signal that is applied to the phase detector of the high frequency phase-locked loop for producing a tracking error signal which is applied to said loop voltage controlled oscillator.
Claim 3
Dependent Claim
59 words
A wide deviation tracking filter as set in forth in claim 1 wherein said digital phase shifter is connected in series in said low frequency phase-locked loop and comprises a D-type flip flop having its clock input connected to the output of the low frequency phase-locked loop voltage controlled oscillator having a frequency at twice the input signal frequency.
Claim 4
Dependent Claim
30 words
A wide deviation tracking filter as set forth in claim 2 which further includes an exclusive OR circuit in the signal path of said pair of quadrature clock signal outputs.
Claim 5
Dependent Claim
36 words
A wide deviation tracking filter as set forth in claim 2 which further includes a delay gate connected in series in each of the pair of quadrature clock output signal paths from said D-type flip flop.
Claim 6
Dependent Claim
33 words
A wide deviation tracking filter as set forth in claim 1 wherein said stable oscillator and said loop voltage controlled oscillator in said high frequency phase-locked loop are both low phase noise oscillators.
Claim 7
Dependent Claim
26 words
A wide deviation tracking filter as set forth in claim 5 wherein said low phase noise oscillators are crystal oscillators operating at or near 10 megahertz.
Claim 8
Dependent Claim
33 words
A wide deviation tracking filter as set forth in the claim 1 wherein said high frequency phase-locked loop comprises a first power divider, coupled to the output of said loop voltage control oscillator.
Claim 9
Dependent Claim
38 words
A wide deviation tracking filter as set forth in claim 7 wherein said image rejection means in said high frequency phase-locked loop comprises a second power divider having a pair of in phase outputs coupled to said mixers.
Claim 10
Dependent Claim
42 words
A wide deviation tracking filter as set forth in claim 8 wherein said image rejection means comprises a quadrature hybrid circuit coupled to the outputs of said mixers and to the input of the phase detector of said high frequency phase-locked loop.
References Cited (Backward Citations)
US4352074A
Cited
US4453137A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-20 | 1992-09-19 | 1993-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-20 | 1996-09-19 | 1997-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-20 | 2000-09-19 | 2001-03-21 | $7700.00 | Window Closed / Lapsed |