US5075639A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Plural phase locked loop circuit suitable for integrated circuit
Assignee: Oki Electric Industry Co Ltd
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Filing: 1991-05-23
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Granted: 1991-12-24
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Expires: 2011-05-23
Abstract
Abstract A PLL circuit suitable for fabrication into an integrated circuit includes: a first phase comparator for determining a phase difference between an input signal and a first feedback signal to produce a first phase difference signal in rsponse to the phase difference; a first loop filter for removing a high frequency constituent from the first phase difference signal; a first variable frequency oscillator which oscillates at a frequency which varies in response to an output of the first loop filter to produce the first feedback signal; a second phase comparator for determining a phase difference between a reference signal and a second feedback signal to produce a second phase difference signal in response to the phase difference; a second loop filter for removing a high frequency constituent from the second phase difference signal; a second variable frequency oscillator having substantially the same characteristics as those of the first variable frequency, oscillator which oscillates at a frequency which varies in response to an output of the second loop filter to produce the second feedback signal, and a signal adder for adding the outputs from the first and second filters and for applying the added signal to the first variable frequency oscillator.
Inventors
- 👤 Takashi Taya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:49
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03L7/07; H03L7/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
250 words
A phase-locked loop circuit comprising: a first phase comparator for receiving an input signal and for determining a phase difference between the input signal and a first frequency signal to produce a first phase difference signal indicative of the phase difference therebetween; a first loop filter connected to said first phase comparator for eliminating a high frequency component from the first phase difference signal; a second phase comparator for receiving a reference signal and for determining a phase difference between the reference signal and a feedback signal to produce a second phase difference signal indicative of the phase difference between the reference signal and the feedback signal; a second loop filter connected to said second phase comparator for eliminating a high frequency component from the second phase difference signal; a signal adder circuit connected to said first and second loop filters for adding outputs from said first and second loop filters; a first variable-frequency oscillator operative in response to said signal adder circuit for producing the first frequency signal as an output of said loop circuit at a first frequency associated with an output from said signal adder circuit; a second variable-frequency oscillator operative in response to said second loop filter for producing a second frequency signal at a second frequency associated with the output from said second loop filter; and a frequency divider connected to said second variable-frequency oscillator for dividing the second frequency of the second frequency signal to produce the feedback signal to said second phase comparator.
Claim 2
Dependent Claim
250 words
A phase-locked loop circuit comprising: a first phase comparator for receiving an input signal and for determining a phase difference between the input signal and a first frequency signal to produce a first phase difference signal indicative of the phase difference therebetween; a first loop filter connected to said first phase comparator for eliminating a high frequency component from the first phase difference signal; a second phase comparator for receiving a reference signal and for determining a phase difference between the reference signal and a feedback signal to produce a second phase difference signal indicative of the phase difference between the reference signal and the feedback signal; a second loop filter connected to said second phase comparator for eliminating a high frequency component from the second phase difference signal; a signal adder circuit connected to said first and second loop filters for adding outputs from said first and second loop filters; a first variable-frequency oscillator operative in response to said signal adder circuit for producing the first frequency signal as an output of said loop circuit at a first frequency associated with an output from said signal adder circuit; a second variable-frequency oscillator operative in response to said second loop filter for producing a second frequency signal at a second frequency associated with the output from said second loop filter; and a frequency divider connected to said second variable-frequency oscillator for dividing the second frequency of the second frequency signal to produce the feedback signal to said second phase comparator.
Claim 3
Dependent Claim
31 words
A phase locked loop circuit in accordance with claim 1, wherein said frequency divider comprises a variable frequency divider capable of changing its dividing ratio in accordance with signals input thereto.
Claim 4
Dependent Claim
72 words
A PLL circuit in accordance with claims 1 or 2, wherein said first variable frequency oscillator comprises a current-controlled oscillator which oscillates at a frequency in response to an output current from said first loop filter to develop the first frequency signal; said second variable frequency oscillator comprising a current-controlled oscillator which oscillates at a frequency in response to an output current from said second loop filter to develop the feedback signal.
Claim 5
Dependent Claim
24 words
A PLL circuit in accordance with claims 1 or 2, wherein each of said first and second phase comparators comprises a balanced chopper circuit.
Claim 6
Dependent Claim
24 words
A PLL circuit in accordance with claims 1 or 2, wherein each of said first and second phase comparators comprises a balanced modulator circuit.
Claim 7
Dependent Claim
40 words
A PLL circuit in accordance with claims 1 or 2, wherein each of said first and second phase comparators comprises a phase frequency comparison circuit which receives two input signals and determines a phase difference and a frequency difference thereof.
Claim 8
Dependent Claim
39 words
A PLL circuit in accordance with claim 1, wherein said first and second phase comparators, first and second loop filters, first and second variable frequency oscillators, signal adder circuit and frequency divider are formed on a single semiconductor chip.
Claim 9
Dependent Claim
22 words
A PLL circuit in accordance with claim 3, wherein each of said first and second phase comparators comprises a balanced chopper circuit.
Claim 10
Dependent Claim
22 words
A PLL circuit in accordance with claim 3, wherein each of said first and second phase comparators comprises a balanced modulator circuit.
Claim 11
Dependent Claim
38 words
A PLL circuit in accordance with claim 3, wherein each of said first and second phase comparators comprises a phase frequency comparison circuit which receives two input signals and determines a phase difference and a frequency difference thereof.
Claim 12
Dependent Claim
184 words
A phase locked loop circuit in accordance with claim 1, wherein said first phase comparator comprises an exclusive-OR gate having two input terminals for respectively receiving said external input signal and said first frequency signal; wherein said second phase comparator comprises an exclusive-OR gate having two input terminals for respectively receiving said reference signal and said feedback signal; wherein said first and second loop filters each comprises a low pass filter including a resistor and a capacitor; wherein said signal adder circuit comprises two resistors, each resistor having first and second terminals, said respective first terminals receiving said outputs of said first and second loop filters, and an operational amplifier having an input terminal which is commonly connected to said second terminals of said two resistors; wherein said first variable frequency oscillator comprises a multivibrator type voltage-controlled oscillator which is driven by said output of said first loop filter for producing said first frequency signal; and wherein said second variable frequency oscillator comprises a multivibrator type voltage-controlled oscillator which is driven by said output of said second loop filter for producing said feedback signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-23 | 1995-06-24 | 1995-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-23 | 1999-06-24 | 1999-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-23 | 2003-06-24 | 2003-12-24 | $7700.00 | Window Closed / Lapsed |